What do you think of Incisive Unified Simulator vs. VCS

[tybhsl]

incisive unified simulator

What do you think of Incisive Unified Simulator of Cadence vs VCS of synopsys? Thanks!

 

[nanako]

cadence incisive unified simulator

in what area you wish to compare the two. the 2 products are no long just a simulator already. they have packed in so many features like assertion, coverage, etc in it.

 

[z81203]

systemc simulation in vcs simulator

just NC vs VCS.
NC stable, VCS faster.

 

[nanako]

ldv systemverilog

VCS faster only in RTL. In gate level netlist simulation, NC still has the edge.

 

[cnspy]

vcs comparable tool in cadence

Does the IUV support systemverilog?

 

[spauls]

incisive vs vcs

yes it supports system verilog

 

[nand_gates]

ius vcs modelsim

IUV systemVerilog support is no good!
VCS is too good if you wish to do SystemVerilog!

 

[Kulprashant]

incisive unified simulator psl

hi,
vcs doesn't support verification using psl/sugar and systemc.whereas cadence unified simulator will support.

with regards,
kul

 

[nanako]

comparing ius with vcs

it depends on what language you are using in design and verification. Pure verilog, both also no problem.

systemverilog in design and assertion, VCS is the one.

verilog and sugar as assertion, IUS as the one.

 

[Arnold]

cadence incisive unified simulator ldv

VCS's new version will support SystemC, IUS's support for systemverilog is bad!

 

[arunragavan]

systemc and systemverilog vcs support

when compare with cadence LDV and NCverilog , synopsys VCS7 is better.
read deepchip.com reviews
about both LDV , NCverilog and VCS. VCS is better than other simulation from cadence.
but globally accepted simulation tool is modelsim

 

[soccer]

gate level simulation ius

VCS & IUS are both simulation tools. VCS's new version supports SystemC and systemverilog now, IUS's support for systemverilog is bad!

 

[Arnold]

simulation profile vcs

IUS is not just a simulator any more.

 

[jjww110]

incisive unified simulator

use vcs for rtl simulation and use nc for gate level simulation