What can I do to this message

[taolibuyan]

Xilinx ISE 8.1i gives me this message:

INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <vid_byp_reg1<0>> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.

(This message repeats for every bit of vid_byp_reg1.)

The related codes are:

always @(posedge mclk_p or posedge rst)
begin
if (rst) vid_byp_reg1[9:0] <= #(1) 10'b0;
else if (pclk_en) vid_byp_reg1[9:0] <= #(1) vdi_reg[9:0];
end

always @(posedge mclk_p or posedge rst)
begin
if (rst) vid_byp_reg2[9:0] <= #(1) 10'b0;
else if (pclk_en) vid_byp_reg2[9:0] <= #(1) vid_byp_reg1[9:0];
end

always @(posedge mclk_p or posedge rst)
begin
if (rst) vid_byp_reg3[9:0] <= #(1) 10'b0;
else if (pclk_en) vid_byp_reg3[9:0] <= #(1) vid_byp_reg2[9:0];
end

..............

Does this message mean I can simply remove the reset statement? Why does this message only occur for vid_byp_reg1, not for the other registers?

The program is using more than 100% of resources. So it would be great to reduce the slices the register uses. Thanks.

 

[echo47]

That XST info message is advising you that it could move those flops into an SRL16 if you could eliminate the reset logic. Don't remove the reset logic if your design requires it.

XST uses SRL16's to efficiently implement serial-in serial-out shift registers. If your design doesn't have any more similar structures, then you probably won't get any more of those particular info messages.