What are the maximum W and L CMOS sizes of a gate?

[MikeR]

What values of length and width of a gate it is possible to choose?
Whether I can for example at 0.18 technology choose width of the channel 0.21?

 

[evilguy]

Re: CMOS size

you can use any width as long as it permit by your fab process. you can refer to their documentation what minimum and maximum transistor size you can use. As mosis lamba design rule, the minimum geometry is 3/2.

 

[rajkumaru]

Re: CMOS size

Hi,
For digital/standard cell design generally we take the length of transistor is same as technology. For Example-- in .18u technology length shouldbe fix as .18u.
But in analog design, we can take length of transistor 2 to 5 times of technology.
as example-- in .18u technology length can be anything from .18u- to- .90u

for fixing width, we can go through the document provided by the foundary. where a matrix will be define by saying that upto what extent we can choose the width of transistor for particular technology.

 

[MikeR]

Re: CMOS size

Thanks that have answered.
Rajkumaru, me analog development interests.
Who can tell to me, or give the reference, what values are length/width
Allow to choose concrete those processes?
Rajkumaru, you write that at 0.18 I can choose technologies length between 0.18 and 0.9, OK.
But with what step I can do it, through 0.01 (0.19,0.2,0.21.....) or through 0.02 (0.2,0.22,0.24.....)
Here what exactly me interests. I already searched for similar materials on www.mosis.com but yet have not found.
Can prompt where I should address.

 

[waxtomato]

CMOS size

find the limits in you Spice files

 

[MikeR]

Re: CMOS size

find the limits in you Spice files

Tell please, how?

 

[rameshabng]

Re: CMOS size

open the model file ur using for the transistor. there u will get lmin and Wmin

 

[rajkumaru]

Re: CMOS size

Foundry provide few document with model file this contain few pdf file also, in which you can get size matrix of mos and other helpful information also.

 

[evilguy]

Re: CMOS size

it is all depend on foundry process. what process this you use? if you use mosis, they use lambda rule to map it to actual fab process. so instead of micron, the use lambda.

 

[raduga_in]

CMOS size

The minimum width that you can choose is usually governed by the contact size between the source and drain region and the metal 1.