What are the CDR lock requirements?

[faizalism]

Dear All,

I am designing the 8Gbps clock data recovery circuit. My VCO center frequency is 4GHz and the tuning range is between 4GHz to 3.2GHz. And my loop bandwidth is 4MHz. I have simulated 8Gbps as the data rate, and my cdr can locked the input. Then, i tried to changed the input data rate to 7.8Gbps and surely it failed to lock because data input and clock difference is too large; larger than bandwidth. Or the cdr can locked?

The question is, how to simulate for difference input data rate and the cdr will locked the input. Maybe I need to use .step parameter or ... other command? FYI, I am using eldo to simulate the circuit.

 

[Btrend]

cdr loop bandwidth

My VCO center frequency is 4GHz and the tuning range is between 4GHz to 3.2GHz.

I got 2 question :
(1) why center freq. is 4GHz and tuning range is 4G to 3.2G ?
if 4G was center freq. then tuning range should cover freq. range from less 4G to higher 4G, is it correct ?
(2) the VCO has only 4GHz maximam but your input is 8GHz, so you have a divider between output of VCO and PFD, is it correct ?

 

[faizalism]

Re: CDR lock requirement

Dear Btrend,

1) Sorry, for the tuning range it is between 3.2 GHz - 4.5 GHz.
2) Actually my input is 8Gbps which is equivalent to 4GHz. Because I used NRZ data input.

So, do you have any tips.

Thanks,

 

[faizalism]

Re: CDR lock requirement

Dear All,

Any ideas.....? Or maybe you all can give any hints..

Thanks

 

[gdhp]

CDR lock requirement

1: For 7.8Gbps input data, and to correctly latch, the clock is 3.9GHz, it is between your VCO range. So why it can't be locked?

2: how to consider the bandwidth of the cdr ?

 

[edajason]

Re: CDR lock requirement

Bandwidth of the CDR is trade-off between jitter transfer and input jitter tolerance if linear phase detector used. A difficult task.

1: For 7.8Gbps input data, and to correctly latch, the clock is 3.9GHz, it is between your VCO range. So why it can't be locked?

2: how to consider the bandwidth of the cdr ?

 

[faizalism]

Re: CDR lock requirement

Dear gdhp,

1. IF u directly test the input with 7.8Gbps (3.9GHz), and then your center frequency is 4GHz. Are you sure the CDR can locked the data? Or do you mean, by simulating first with 8Gbps then reducing the data rate to 7.8Gbps? ....then how to reduce the input data rate in simulation?

2. While for bandwidth, you can calculate the bandwidth by this formula , w = Kpd * Kvco * Icp * R (ref: Jafar Savoj paper)

Help me if I am wrong.

Thanks,

 

[gdhp]

CDR lock requirement

HI faizalism
i see. i think your cdr loop has very narrow frequency deviation lock ability.
For double-loop, it is not a problem.

 

[beckchm]

Re: CDR lock requirement

good