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These are used in the model files to simulate the MOS for the corner conditions.
for slow mos, the thresold voltage is increased and for fast MOS, the thresold voltage is decreased. Other variations could be tox, junction capacitances..etc
It is more to the process variation, the designed circuitry should be well operated in all of this condition in a satisfactory output prior to GDSII submission
Hence use the process corner parameters (which models the FF, FS, SF, SS) and then verify the circuit.
But this now increases the number of testing in exponentially (exponent = 4). Therefore it is illogical and waste of time. So how to determine which oprational mode and/or transistor can be affected by each and every process corners? If it is not clear: For every FF...SS, there is some inteneded operation is being affected (due to change in transistor characteristics). How to spot them? REply if you have done before. Thanks in advance.
Srivats
These are just cornercases. As you know, processes have tolerances from wafer to wafer and even over one wafer. These changes result in different Cox, Vth, tox, .... The process has upper and lower limits for every one of these parameters. The slow model is the transistor model, where every parameter is at its limit where it makes the transistor the slowest. The fast model is exactly the opposite.
In real life you would probably never get into these extreme corner cases. These are only error checks, mostly used by digital designers to test their gates under any possible circumstance.
Well, I was just curious how these process corners affect my analog circuit? i understand more of those process corners.. finally, if anyone has found any kind of relationship between those corners and analog circuits.. let me know. thanks in advance.
thanks for all those replies.
srivatsan
Generally, most of the effects that can be occurred due to process corner appear at the digital circuits design. If you need to design a fast digital circuit, you should take care for the effect of slow corner (for both NMOS and PMOS).
Their effect on analog circuits will appear and become effective if you are biasing your transistors at the weak inversion region (i.e. the MOSFET channel is not fully inverted or accomplished). So take care of the regions where you are biasing your transistors.
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