Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What are different layer optimization techniques in VLSI for lower nodes?

Status
Not open for further replies.

Girija_123

Newbie level 5
Joined
Aug 3, 2022
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
53
Will you please let me know What are different layer optimization techniques in VLSI for low power nodes?
 

I can't make sense of this question. What is a layer technique?
This was also interview question, Probably interviewer might be thinking about layer promoting from lower layer to higher metal layer, so that we can see timing improvement for violated setup paths.
 
Last edited:

This was also interview question, Probably interviewer might be thinking about layer promoting from lower layer to higher metal layer, so that we can see timing improvement for violated setup paths.
that sounds very strange. maybe the interviewer wanted to go in the direction of non-default rules but the wording os very strange.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top