What affect the power dissipation based on layout level?

[wolfrain]

At this moment I am doing a Op Amp Layout, and successfully have gone through the LVS with no parasitics. It's working fine with the schematic.

Right now I am thinking the power dissipation. What really matters in the power dissipation point of view? For what I have done now for the first version is just to minimize the whole stuff area without thinking the power issue. But I want to think of another way to implement such a Op Amp, and probably, for lower power than the current design I just finished.

So far, I am still thinking how to arrange the position of all these PMOS ,NMOS, resistor, capacitor to build up the second version. But still, no further idea.

So, any ideas??

Thanks in advance.

 

[BackerShu]

For low power. I don't think there is big stuff we can do at layout level. To minish the parasitic cap may give some improvment, but it's still trivial. So I think sechmatic should be modified if low power is taken into account.

For arranging the components. I think avoiding the crosstalk between AC signal(or dynamic signal) is the most important.

Just some immature advice.

 

[EmbdASIC]

Althought careful layout is key to analog design, but i think for power estimation standard techniques if any are more for clock routing, logic style based, e.g branch based logic etc. which are basically not really applicable in your context.


Regards

 

[erikl]

... how to arrange the position of all these PMOS ,NMOS, ...

You probably wouldn't want to separate your output transistors too far from each other. So the best thing you can do is to position your input transistors so symmetrically, that the thermal flow from the output transistors reaches them equally (i.e equal distances). This would guarantee min. (thermal generated) input offset for your opAmp.

 

[wolfrain]

Thank you all~

I will try it

 

[wolfrain]

Sorry guys, I got another silly question.

I try to sweep the value of the component, let's say, the rpolyh from the analoglib. For the rpolyh, we have resistance, width and length. At this moment, I am doing a filter using Op Amp and rpolyh and cpoly, and what I want is to operate a parametric analysis on the rpolyh, for which I only want to sweep the resistance. But after I put pPar("R") in its properties--resistance option, run the analysis and plot the result, the curves appear to be the same, which I suppose the width and lengh of the rpolyh do not change during the parametric analysis though the resistance value changes.



Oh, one more question. If I want optimal Resistance and Capacitance, both in values, which meet my project specification, and size, which can reduce the total size of the design layout, so how to do the analysis and plot something like values versus size curve, and then comes to a optimal point that both satisfy what I want.

Thank you in advance.
Regards,
wolfrain

 

[erikl]

Re: Parametric resistance simulation on rpolyh

For the rpolyh, we have resistance, width and length. At this moment, I am doing a filter using Op Amp and rpolyh and cpoly, and what I want is to operate a parametric analysis on the rpolyh, for which I only want to sweep the resistance. But after I put pPar("R") in its properties--resistance option, run the analysis and plot the result, the curves appear to be the same, which I suppose the width and lengh of the rpolyh do not change during the parametric analysis though the resistance value changes.

I guess the primary parameters of rpolyh are width and length, the resistance R is just a secondary (calculated) parameter, so you probably cannot set it as parameter in the simulation. Take a fixed W and use L as your simulation parameter.