dayana42200
Junior Member level 3
Dear all.
Im currently synthesizing a design using Xilinx ISE. 14.7
Based on the warning below, it says that ALL the sub module is
unconnected.
This the verilog code for the top module that I currently synthesis.
AND this the submodule verilog code based on the above top module and
RTL diagram with no warning (attached).
Did I wrote the coding wrong?
Thank you very much
Im currently synthesizing a design using Xilinx ISE. 14.7
Based on the warning below, it says that ALL the sub module is
unconnected.
Code dot - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 WARNING:Xst:1290 - Hierarchical block <CompInterA> is unconnected in block <A>. It will be removed from the design. WARNING:Xst:1290 - Hierarchical block <DeltaV> is unconnected in block <pe_block[0].pe.pe0>. It will be removed from the design. WARNING:Xst:1290 - Hierarchical block <DeltaIx> is unconnected in block <pe_block[0].pe.pe0>. It will be removed from the design. WARNING:Xst:1290 - Hierarchical block <DeltaIy> is unconnected in block <pe_block[0].pe.pe0>. It will be removed from the design. WARNING:Xst:1290 - Hierarchical block <DeltaH> is unconnected in block <pe_block[0].pe.pe0>. It will be removed from the design. WARNING:Xst:1290 - Hierarchical block <CompInterA> is unconnected in block <A>. It will be removed from the design. WARNING:Xst:1290 - Hierarchical block <DeltaV> is unconnected in block <pe_block[1].pe.pe1>. It will be removed from the design. WARNING:Xst:1290 - Hierarchical block <DeltaIx> is unconnected in block <pe_block[1].pe.pe1>. It will be removed from the design. WARNING:Xst:1290 - Hierarchical block <DeltaIy> is unconnected in block <pe_block[1].pe.pe1>. It will be removed from the design. WARNING:Xst:1290 - Hierarchical block <DeltaH> is unconnected in block <pe_block[1].pe.pe1>. It will be removed from the design. WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/DeltaH> of block <Sync_Rst_TWO_Input_Sub> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed. WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/DeltaIx> of block <DelTop> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed. WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/DeltaV> of block <Sync_Rst_TWO_Input_Sub> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed. WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/DeltaH> of block <Sync_Rst_TWO_Input_Sub> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed. WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/DeltaIx> of block <DelTop> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed. WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/DeltaV> of block <Sync_Rst_TWO_Input_Sub> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed. WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/A/CompInterA> of block <Sync_Rst_CompInter> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed. WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/A/CompInterA> of block <Sync_Rst_CompInter> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed. WARNING:Xst:2973 - All outputs of instance <pe_block[0].pe.pe0/DeltaIy/DeltaLeftSubtract> of block <Sync_Rst_TWO_Input_Sub> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed. WARNING:Xst:2973 - All outputs of instance <pe_block[1].pe.pe1/DeltaIy/DeltaLeftSubtract> of block <Sync_Rst_TWO_Input_Sub> are unconnected in block <SystolicArrayNovelty2>. Underlying logic will be removed.
This the verilog code for the top module that I currently synthesis.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 module SystolicArrayNovelty2(Clk,Rst,SubSec,QueSec,PDeltaH,PreDeltaIy,SubSecOut ); parameter ComputeDataWidth = 8; parameter PE = 2; //LENGTH parameter QC = 2; //QC bit size input Clk,Rst; input [QC-1:0] SubSec; input wire [(PE*QC)-1:0] QueSec; input [ComputeDataWidth-1:0] PreDeltaH,PreDeltaIy; output [QC-1:0] SubSecOut; wire [ComputeDataWidth-1:0] h [PE-1:0]; wire [ComputeDataWidth-1:0] l [PE-1:0]; wire [PE*3-1:0] SSout; genvar i; generate for (i=0; i < PE; i = i + 1) begin : pe_block if (i == 0) //first processing element in auto-generated chain begin:pe ProcessingElementNovelty2 pe0 ( .Clk (Clk), .Rst (Rst), .SS (SubSec[1:0]), .QC (QueSec[1:0]), .PreDeltaH (PDeltaH), .PreDeltaIy (PreDeltaIy), .DelH (h[i]), .DelIy (l[i]), .SS_Out (SSout[1:0]) ); end else //processing elements other than first one begin:pe ProcessingElementNovelty2 pe1 ( .Clk (Clk), .Rst (Rst), .SS (SSout[(2*i)-1:(2*i)-2]), .QC (QueSec[(2*i)+1:(2*i)]), .PreDeltaH (h[i-1]), .PreDeltaIy (l[i-1]), .DelH (h[i]), .DelIy (l[i]), .SS_Out (SubSecOut) ); end end endgenerate endmodule
AND this the submodule verilog code based on the above top module and
RTL diagram with no warning (attached).
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 `timescale 1ns / 1ps module ProcessingElementNovelty2(Clk,Rst,SS,QC,PreDeltaH,PreDeltaIy, DelH,DelIy,SS_Out); parameter ComputeDataWidth = 8; localparam N_A = 2'b00, //nucleotide "A" N_C = 2'b01, //nucleotide "C" N_G = 2'b10, //nucleotide "G" N_T = 2'b11; //nucleotide "T" input Clk,Rst; input [1:0] SS,QC; input signed [ComputeDataWidth-1:0] PreDeltaH,PreDeltaIy; output signed [ComputeDataWidth-1:0] DelH,DelIy; output [1:0] SS_Out; wire signed [ComputeDataWidth-1:0] a,DelIx,DelV; IntermediateA #( .ComputeDataWidth (ComputeDataWidth)) A ( .Rst (Rst), .SUBJECT_SEQUENCE (SS), .QUERY_CHARACTER (QC), .DelIx_i_1_j (DelIx), .DelIy_i_j_1 (PreDeltaIy), .SCORE_InterA (a), .SUBJECT_SEQUENCE_OUT (SS_Out) ); Sync_Rst_TWO_Input_Sub #( .ComputeDataWidth (ComputeDataWidth)) DeltaH ( .Clk (Clk), .Rst (Rst), .A (a), .B (DelV), .AdditionOUT (DelH) ); Sync_Rst_TWO_Input_Sub #( .ComputeDataWidth (ComputeDataWidth)) DeltaV ( .Clk (Clk), .Rst (Rst), .A (a), .B (PreDeltaH), .AdditionOUT (DelV) ); DelTop #( .ComputeDataWidth (ComputeDataWidth)) DeltaIx ( .Clk (Clk), .Rst (Rst), .InterA (a), .PreDelH (PreDeltaH), .SCORE_DelTop (DelIx) ); DelLeft #( .ComputeDataWidth (ComputeDataWidth)) DeltaIy ( .Clk (Clk), .Rst (Rst), .InterA (a), .PreDelIy_i_j_1 (PreDeltaIy), .PreDelV (DelV), .SCORE_DelLeft (DelIy) ); endmodule
Did I wrote the coding wrong?
Thank you very much
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