Warnning of short-circuited terminals in VIRTUOSO - LVS error

[mohamis288]

Hello,

in my layout, I have flattened a single transistor and changed its connections in order to make two transistors from aforementioned transistor. here is the image of this section:

but in LVS window, I receive error related to short-circuited terminals. here this is:

I do want those terminals in image be connected. after analyzing my circuit, I understood that because of flattening mentioned transistor, the order of some source and drain terminals has changed, and also, they have a particular terminal name which are not allowed to be connected to other terminals. because of mentioned reason, three of my PIN in the LVS cannot be matched to schematic. how can I overcome this problem (I hope I am not supposed to change the terminal name of each path one-by-one.)

 

[jjx]

Not supereasy to see from your pictures, but isn't it due to the D label being still there after flattening. (How did you do the flattening, and why?). Can you search for the D labels, and remove them?

 

[dick_freebird]

If you have a clean extracted view then use probes to find the short (whether by name or by metal). You might also inspect for things like rogue contact / via / plain metal bits that have landed where they cause a short in fact. Zoom in to where you can see any bridging of stripe gaps and wander around with those probes lit up, and look for anything that is not all ortho and uniform width.

You could make selectable only the metalX/pin layers (if you used ploygon pins) and find any strays easily with ctrl-A (select all).

If you are convinced that the layout is clean, maybe removing all pins and hand placing the ones you really want, where you really want them, is the quickest and cleanest way out.