Warning TIM-141 during synthesis (Design compiler)

[stevenv07]

Hello everyone,

When I synthesized my design using Synopsys Design Compiler, I found some warnings as follows:
Warning: Gated clock latch is not created for cell 'tx0/....' on pin 'B3' in the design 'tx_....' (TIM-141).

Could you show me how to solve this warning? and what is the reason?

Thanks so much~
Steven

 

[ThisIsNotSam]

type 'man TIM-141' in DC's terminal, it should give you a hint of what is going on.