walking 1/0 test for memory bist

[MEDIPALLY NAVEEN KUMAR]

hi all....

i am doing a project on built in self repair for rams.Can u please suggest me which algorithm i have to use for it and why that only?
if it is walking 1/0 test how it is different from others and why we choose it?

please give response as soon as possible..
thanqqqqq

 

[ivlsi]

very interesting... do you should test address lines as well as data ones?

 

[dll_fpga]

walking 1/0 pattern is used to check the integrity of the address bus and to detect that decoding logic is working properly....this is done for larger memories where it is not possible to test 2^n combinations....other patterns are 'hAA,'h55 .hope u got it

hi all....

i am doing a project on built in self repair for rams.Can u please suggest me which algorithm i have to use for it and why that only?
if it is walking 1/0 test how it is different from others and why we choose it?

please give response as soon as possible..
thanqqqqq

 

[amberyn]

0/1 walking is the sample algorithm, so it just can be used for some sample fault checking, if you want more, suggestions is "march C", while the algorithm you can search some reference documents or reference my paper, but it's writen in chinese.

 

[ivlsi]

What's the exact name of the algorithms? Thank you!

 

[amberyn]

"March C"
used algorithms used by MBIST are :
(1) March C+ (or March2), targeting at stuck-at, transition and coupling
(2) Checkerboard / Inverse Checkboard, targeting at neighborhood sensitivity

Check detailed information from BIST IP venders (like Mentor Graphics, Synopsys etc.).
The March C algorithm, and its modifications, is a popular algorithm for memory testing. This algorithm, which consists of 11 operations (11n), writes and reads words of 0s, followed by writing/reading words of 1s, in both descending and ascending address spaces.

The original March C algorithm consists of the following steps:

1. Write 0s to all locations starting at the lowest address (initialization).
2. Read 0 at lowest address, write 1 at lowest address, repeating this series of operations until reaching the highest address.
3. Read 1 at lowest address, write 0 at lowest address, repeating this series of operations until reaching the highest address.
4. Read 0 from the lowest address to the highest address.
5. Read 0 at highest address, write 1 at highest address, repeating this series of operations until reaching the lowest address.
6. Read 1 at highest address, write 0 at highest address, repeating this series of operations until reaching the lowest address.


March C- : The algorithm modifies the March C algorithm by eliminating the redundant Read 0 operation between the ascending and descending address operations. Removing this operation reduces the algorithm from 11n to 10n, without sacrificing any fault coverage.


March C+ : The algorithm modifies the original March C algorithm by adding an extra read operation after each stage of the march. While increasing the algorithm from 10n (for the March C-) to 13n, this extra read allows additional fault detection, most notably, stuck-open faults for all types of RAM. It's also possible to add one more read operation at the end of the final stage, which increases the algorithm from 13n to 14n (commonly referred as March 14n).

Varying Data Backgrounds
The March C+ algorithm normally writes and reads words of either all 0s or all 1s. However, you can vary the value the March C+ test uses for each write/read operation. By varying the data values, or data backgrounds, you can increase the fault detection. For example, by intelligently choosing the data background from inductive fault analysis of the memory, the enhanced algorithm can detect state coupling faults between two cells of the same address, for which the March C+ algorithm cannot normally prove detection.