liu_uestc
Junior Member level 1
hi, guys
i'm a icer.
7years digital ic design experiences.
7years professional digital ic verification experiences.
familarize:
verilog, systemverilog, vmm ,uvm ,xml ,perl ,c ,c++ ,design pattern ,csh ,vcs ,modelsim,and so on
specially, i familarize the source code of vmm and uvm and will finished works for you followed the first rate verification technology.
area:
tcp/ip ,network interface ,switch ,ddr ,pcie ,usb ,spi ,uart ,cpu, mcu ,vpn ,firewall , fpga ,and so on
now i'm wanting for a outsoursing chance strongly.
info:
mail: liu_uestc@163.com
msn: liu_uestc@hotmail.com
qq: 10863523
i'm a icer.
7years digital ic design experiences.
7years professional digital ic verification experiences.
familarize:
verilog, systemverilog, vmm ,uvm ,xml ,perl ,c ,c++ ,design pattern ,csh ,vcs ,modelsim,and so on
specially, i familarize the source code of vmm and uvm and will finished works for you followed the first rate verification technology.
area:
tcp/ip ,network interface ,switch ,ddr ,pcie ,usb ,spi ,uart ,cpu, mcu ,vpn ,firewall , fpga ,and so on
now i'm wanting for a outsoursing chance strongly.
info:
mail: liu_uestc@163.com
msn: liu_uestc@hotmail.com
qq: 10863523