Ivan_Ryger
Junior Member level 1
Dear colleagues,
I am trying to design a small BCD counter that outputs its value via SPI interface.
The speed of the BCD counter is not critical, it reads an incremental sensor.
The faster part of my design is the SPI interface that runs at a couple tens of kHz.
After studying the concepts of clock domain crossing from fpga4fun webpage, i introduced a FIFO between the slow and fast clock domain in order to synchronize them.
For testing the idea instead of sensor I generate a slow clock by dividing the master clock like this:
afte trying to implement the design, I get the following message:
Please has anyone encountered this problem? At least I will need to be directed what to look for or how to interpret the compiler message.
Thank you.
I am trying to design a small BCD counter that outputs its value via SPI interface.
The speed of the BCD counter is not critical, it reads an incremental sensor.
The faster part of my design is the SPI interface that runs at a couple tens of kHz.
After studying the concepts of clock domain crossing from fpga4fun webpage, i introduced a FIFO between the slow and fast clock domain in order to synchronize them.
For testing the idea instead of sensor I generate a slow clock by dividing the master clock like this:
Code:
wire divclk, clk_slow;
reg [26:0] divider;
// clock divider
always @(posedge clk)
divider <= divider + 1;
assign divclk = divider[17]; // divided clock for SPI controller
assign clk_slow = divider[26]; // divided clock for the counter
afte trying to implement the design, I get the following message:
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets enable_IBUF] >
enable_IBUF_inst (IBUF.O) is locked to IOB_X0Y61
and enable_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
Please has anyone encountered this problem? At least I will need to be directed what to look for or how to interpret the compiler message.
Thank you.