Virtuoso hierarchical layout design

[tromeros]

Hi to all! I have the following problem.

I made a layout component in Virtuoso that is simply a stack of metals with vias between them.

When I use this component in my main layout design in order to connect two metals the connectivity checker shows that they are not connected.

Is there something I am missing?
Thanks in advance.

 

[microchaos]

I think the pins are missing?

 

[k_90]

are you using virtuoso XL?

if so you need to use the correct pcell and without hierarchy when connecting.

 

[kumar_eee]

I agree with K_90, If u are using VXL, then check for correct PCell. Otherwise you will get Error.

 

[tiger888]

Try the "mark" net command in VXL or Virtuoso Turbo.
If it does not work, you'd better check your techfile if the via layer definitions been added.

 

[k_90]

Mark net does exactly what it says on the tin, it marks the net nothing more. To keep connectivity you need to drop a via/contact down from the primatives/cadence library one at a time.