Violation during Synopsys Design compiler

[guest7]

Hello,

I am getting the following warning message:

Warning: No scan equivalent exists for cell g7_reg (dp_2). (TEST-120)

When I trying to read a verilog file and compile it with the scan option to convert the non scan flip flops to scan flip flops.

Following is the script i run in design compiler.

analyze -format verilog -lib LIB5 {s27.v}
elaborate s27 -lib LIB5
max_area 1000
create_clock -name clock -period 20 clock
compile
write -format ddc -output "./s27.ddc"
set_scan_configuration -style multiplexed_flip_flop
compile -scan
report_constraint -all_violator
write -format ddc -output "./s27_tp.ddc"
write -format verilog -output "./s27_tp.v"

An help is appreciated.

Thanks

 

[jaydip]

this means your .lib (target library) does not have scanable cells .. one option is, remove "compile -scan" option from script ...

 

[guest7]

Thanks for the reply. But since I am trying to compute the transition fault coverage of a sequential design with non scan flip flops, I think i need to convert each non scan flip flop to scan flip flop. Please let me know if i am wrong.

Also, can you suggest me which library to use (containing scan cells) and from where I can download.

Thanks a lot.

 

[jaydip]

can you paste your .synopsys.dc_setup file?

 

[infinity711]

I am facing the same problem, even though my target.db has scan flops.

I'd appreciate if I someone told me how to connect the flops to make scan chain.

 

[rca]

check if the pointed element by message, could be made with the current library set, I means, perhap the code describe a set&reset flop, which does not exist in scan version in your library, or other king of limitation.

to go foward, you could exclude this cell of scan.

 

[TonyLS]

Could also indicate that g7_reg is a Latch and not a FF