Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Via size and spacing

rd_dinesh

Member level 1
Joined
May 2, 2023
Messages
36
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
217
I'm designing a power amplifier on an RT6006 board,
I want to place vias in my design, I want to know how we can decide the size and spacing between the vias.
 
for grounding the capacitors(i.e, routing between the layers)
What current? What frequency? There are lots of free tools out there to help you calculate appropriate size. You've given us no inormation. Just search
"Via suze calculator"
 
What current? What frequency? There are lots of free tools out there to help you calculate appropriate size. You've given us no inormation. Just search
"Via suze calculator"
1686926044752.png


1686926228666.png


currents through various capacitors in two different modes of operation.
 
Keep in mind every trace and via adds about 1 Ohm/mm per GHz based on ESL of 0.6 nH/mm for path length.

So be aware why your Vdd noise spikes dV=Ic*dt/C and how damping works in simulations from impulse transitions. ( drivers )

If you do not know how to simulate it. Find out.
 
Last edited:

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top