VIA between MET1 & MET2

[ljy4468]

Hi all,

I have a question about the number of via.

I need to route metal with MET1 & MET2 in parallel for maximizing current capability of metal line. (due to current density rule).
Which is if MET1=1mA/um and MET2=2mA/um, then I'll get 3mA/um if I route metal1&2 in parallel with via.

Then what I wanna ask is how many VIAs is needed?
Should I place VIAs at everywhere such as honeycomb?
Is there no problem if I make VIA at everywhere?

fyi, that line are capable of 6A.

Please give me an advice.
Thanks in advance

 

[erikl]

Should I place VIAs at everywhere such as honeycomb?

First place a tight array of vias everywhere along the lines, then remove every second straight via row in direction of the metal line resp. current flow.

Is there no problem if I make VIA at everywhere?

Not good: this would hinder the current flow.

 

[dick_freebird]

Vias tend to reduce the metal cross-section (at least in
a non-planarized stack). If I am sandwiching layers I will
put only a "balance" line of vias there, not fill the trace
with them.

These 1mA/um, 2mA/um lines are going to need a whole
lot of W to make 6A. You really want a thick metal flow.

 

[Teddy]

a) vias don't carry current laterally. So if you go from your i.e. VDD pad to the transistor (assuming you connect MOS to the VDD rail) you can run big fat metals on top of each other without vias.
b) vias are needed to bring current down to the device and from top metal on io pad to the lower metal. If you want 6A to be carried across the chip you will split it to top metal as 4A and 2A on bottom metal. That means both metals need to be 2000um wide. That means you have to provide enough vias at the IO pad to carry 2A down to Metal 1. Considering 0.3mA/via rule (check your design rules) you will need 2000/0.3~ 6600 vias. Then you have to calculate how much current needs to be fed to each S/D.
c) considering that 6A is probably for DCDC you are in trouble - you need 6A metal for source and 6Ametal for drain side. Total 4000um in parallel (2mm stack + 2mm stack). Since 6A dcdcs die area are about 2.5x2.5mm (max) you are in trouble. Way arround it would be to use top level copper RDL. Also use "triangular" shape metal routes.
d) check the design rules. - SOME technologies allow long or large vias some do not. Some don't even like large via arrays.
e) are you designing for 6A DC?

in any way - it IS fun!

 

[timof]

In all the designs that I have seen - power transistors, power nets, etc. - vias are filling the whole available space between the metals, to provide a solid electrical connection, to reduce thermal resistance, etc.

Depending on how the current is injected / extracted form your power line, and on the ratio between resistances of upper/lower metal and via, current may be crowded either in vias, or in metals, at the edges - these effects can and should be modeled to avoid unpleasant surprises.

If the current is routed to a power switch, and needs to be distributed uniformly over a large area - the problem get much more complicated than simple straight current flow. You need to think about proper layout, fingering, trapezoidal shapes, using thick, low resistive top metal layers, etc.

Vias tend to reduce the metal cross-section (at least in
a non-planarized stack). If I am sandwiching layers I will
put only a "balance" line of vias there, not fill the trace
with them.

I never heard of this effect (but I never dealt with non-planarized processes). Can you point to some references (I can;t find anything relevant on internet)?