VHDL unconstrained arrays

[shaiko]

In VHDL you can do the following assignment :

x <= ( others => '1' ) ;

However,
You cannot compare this way :

if x = ( others => '1' ) then

Is there a way to do it compactly without writing the whole long vector?

if x =  "1111111111111111111111111111111111111111" then

 

[TuAtAu]

Good question, I will like to know that too!

But for me, since "1111111111111111111..." is a constant, will consider to declare CONSTANT in generic or library package named CONSTANT32bit1

then

if x = CONSTANT32bit1 then
..
..
end if;

if y = CONSTANT32bit1 then
..
..
end if;

---etc

 

[TrickyDicky]

either declare a handy constant:

constant ONES : std_logic_vector(x'range) := (others => '1');

if x = ONES then

or create the vector properly:

if x = (x'range => (others => '1') ) then

I think the first one is better.

 

[permute]

IIRC, you can do "x = (x'range => '1')" or "signed(x) = -1"