[SOLVED] VHDL signal assigment problem ?

[ajapyy]

this is my question :

We can use a signal assignment statement with inertial delay to remove pulses that are smaller than a certain width. Using only signal assignment statements, write a code fragment for removing positive pulses that are greater than a certain width.

Thanks eveybody

 

[FvM]

Can we assume that you are asking about synthesizable VHDL?

In this case, there are no "inertial delays" or other simulation related timing statements available, all timing has to be generated by clocks, synchronous registers and suitable logic.

 

[ajapyy]

No, i don't synthesizabe code, just a code for simulate.

 

[TrickyDicky]

this is my question :

I highly doubt this is your question. It sounds like your supervisor or lecturer's question.
Either way, it really doesnt teach you much about VHDL and circuits.

 

[ads-ee]

I highly doubt this is your question. It sounds like your supervisor or lecturer's question.
Either way, it really doesnt teach you much about VHDL and circuits.

Well it seems pretty much that is the state of teaching in some parts of the world, unfortunately we get stuck doing the job those teachers were hired to do. :thumbsdown:

 

[ajapyy]

it could be better if you help me , even don't want to say the answer. but you can say idea that help me and I do rest of it. internet forums are for this purpose not for grandpa advises answers !
anyway I solve it.

 

[mrflibble]

Internet forums are also for sharing the solution for the benefit of other future readers. ;-) So what was your solution?

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Well, the grandpa estimation was right on the money.

Question 5 of this one: https://web.mst.edu/~daryl/classes/cpe318/W01/hwk5.html

And hey, that looks familiar: https://embdev.net/topic/350553

anyway I solve it.

:grin: I've seen exactly that type of reaction before. That usually means "I found a sucker on another forum that gave me the solution".

Anyways, good luck with your career in middle management! :thumbsup:

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