VHDL. rewrite FOR LOOP using FOR GENERATE

[4pi]

Hi there!

i have FOR LOOP (here WIDTH=8, B=3)

for i in 0 to (WIDTH - 1) loop
    if r(i)='1' then
        bcode <= std_logic_vector(to_unsigned(i, B));
    end if;
end loop;

and i have to rewrite it using FOR GENERATE.
This is not work:

for i in 0 to (WIDTH - 1) generate
    bcode <= std_logic_vector(to_unsigned(i, B)) when r(i) = '1';
end generate;

Errors:
Error (10028): Can't resolve multiple constant drivers for net "bcode[2]" at ***.vhd(33)
Error (10029): Constant driver at ***.vhd(33)
Error (10028): Can't resolve multiple constant drivers for net "bcode[1]" at ***.vhd(33)
Error (10028): Can't resolve multiple constant drivers for net "bcode[0]" at ***.vhd(33)

should i write ... <= ... when ... else... ?
But i dont have to do nothing in case r(i)=0.

 

[FvM]

Both codes make no sense. You are writing bcode multiple times without reading it. Insequential code (first variant) multiple writes are legal, but only the last (i = WIDTH - 1) is actually performed. In concurrent code, a signal can't be written more than once.

 

[4pi]

this is priority encoder, i need only one value (last, in sequential code).

in second - so it have to be array?

 

[FvM]

this is priority encoder, i need only one value (last, in sequential code).

O.k. then use sequential code. It doesn't work in concurrent code (generate). If it's only exercise - I'm not interested.

--- Updated Oct 26, 2023 ---

You understand that the priority is resolved in reversed order. Therefore you can write something like
if r(highest index) = '1' then
elsif r(highest index - 1) = '1' then
etc.

 

[kaz1]

Hi there!

i have FOR LOOP (here WIDTH=8, B=3)

for i in 0 to (WIDTH - 1) loop
    if r(i)='1' then
        bcode <= std_logic_vector(to_unsigned(i, B));
    end if;
end loop;

and i have to rewrite it using FOR GENERATE.
This is not work:

for i in 0 to (WIDTH - 1) generate
    bcode <= std_logic_vector(to_unsigned(i, B)) when r(i) = '1';
end generate;

should i write ... <= ... when ... else... ?
But i dont have to do nothing in case r(i)=0.

if i is run-time integer (one value in the range 0-7 at any clock) then you only need to code as follows:

if r(i) = '1' then
   bcode <= std_logic_vector(to_unsigned(i, B));
end if;

no need for loop and certainly no need for generate. But what is r(i) ?

 

[4pi]

In concurrent code, a signal can't be written more than once.

Yes. This is the key! i didnt understand it before.
Yes, it was exercise. And now i know that without IF impossible create a priority encoder!
Done

But what is r(i) ?

input std_logic_vector

 

[kaz1]

A loop is meant for the compiler to unroll. It is just for convenience instead of repeating code. It is not mapped to any loop inside hardware. If you want to know what the compiler sees then unroll it to see each statement. For your case, the compiler sees:

if i = 0 then
bcode <= std_logic_vector(to_unsigned(0, B));
elsif i = 1 then
bcode <= std_logic_vector(to_unsigned(1, B)); ...etc
end if;

Thus bcode is assigned in every line. This is like multiple drivers, and is bad coding. I guess the compiler may be kind and just take the last statement or flag error.

if bcode is indexed such as bcode(i) and so is 2D array then you get bcode(i) assigned per each i value. Then you decide a further selection from the 2D array.

If bcode must be 1D array then you need i to be run time indexing(counter), not a loop index.

On the other hand, generate is also a compile time statement but for telling the tool what to include in synthesis or not, right at start. It is unrelated to loop.