syedimran
Newbie level 1
IN THE LAST PROGRAM STORING DATA IN ARRAY ONE AFTER ANOTHER IS CAUSING PROBLEM .. DATA HAS TO GET STORED IN ONLY ONE LOCATION BUT IT IS GETTING STORED AT MULTIPLE LOCATIONS AFTER FIRST ONE.
PLZ HELP ME...
mistake could be at process statement
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port(
a,b,c: in std_logic;
s,cy: out std_logic);
end entity;
architecture fa of fulladder is
signal d,e,f,g: std_logic;
begin
d<=a xor b;
s<=d xor c;
e<=a and b;
f<=a and c;
g<=b and c;
cy<=e or f or g;
end architecture;
-----------------------------------------------------------------------------------------------
--THIS ONE COUNTS TOTAL NUMDER OR 1'S IN 14 BIT VECTOR a..
library ieee;
use ieee.std_logic_1164.all;
entity existingPEX is
port(
a:in std_logic_vector(13 downto 0); --14 bit input data
s: out std_logic_vector(3 downto 0) ); --4 bit extracted value
end entity;
architecture ar of existingPEX is
signal cs,ss :std_logic_vector(16 downto 1);
component fulladder
port(
a,b,c :in std_logic;
s,cy
ut std_logic);
end component;
begin
ss(16)<='0';
ss(14)<='0';
ss(10)<='0';
A1: fulladder port map(a=>a(1),b=>a(2),c=>a(0),s=>ss(1),cy=>cs(1));
A2: fulladder port map(a=>a(4),b=>a(5),c=>a(3),s=>ss(2),cy=>cs(2));
A3: fulladder port map(a=>a(7),b=>a(8 ),c=>a(6),s=>ss(3),cy=>cs(3));
A4: fulladder port map(a=>a(10),b=>a(11),c=>a(9),s=>ss(4),cy=>cs(4));
A5: fulladder port map(a=>a(13),b=>'0',c=>a(12),s=>ss(5),cy=>cs(5));
A6: fulladder port map(a=>ss(2),b=>ss(3),c=>ss(1),s=>ss(6),cy=>cs(6));
A7: fulladder port map(a=>ss(5),b=>'0',c=>ss(4),s=>ss(7),cy=>cs(7));
A8: fulladder port map(a=>cs(1),b=>cs(2),c=>'0',s=>ss(8 ),cy=>cs(8 ));
A9: fulladder port map(a=>cs(4),b=>cs(5),c=>cs(3),s=>ss(9),cy=>cs(9));
A10: fulladder port map(a=>ss(7),b=>'0',c=>ss(6),s=>s(0),cy=>cs(10));
A11: fulladder port map(a=>cs(6),b=>cs(7),c=>'0',s=>ss(11),cy=>cs(11));
A12: fulladder port map(a=>ss(9),b=>'0',c=>ss(8 ),s=>ss(12),cy=>cs(12));
A13: fulladder port map(a=>cs(8 ),b=>cs(9),c=>'0',s=>ss(13),cy=>cs(13));
A14: fulladder port map(a=>ss(12),b=>ss(11),c=>cs(10),s=>s(1),cy=>cs(14));
A15: fulladder port map(a=>ss(13),b=>cs(12),c=>cs(11),s=>ss(15),cy=>cs(15));
A16: fulladder port map(a=>cs(14),b=>ss(15),c=>'0',s=>s(2),cy=>cs(16));
s(3)<=cs(13) or cs(15) or cs(16);
end architecture;
-----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cam_ones_count is
port (
RorW : in std_logic; --read or write--
data : in std_logic_vector(13 downto 0); --input data--
adrs : out std_logic_vector(13 downto 0); --output data--
PorA : out std_logic); -- searched data present or apsent
end entity;
architecture arc of cam_ones_count is
signal count1: integer:=1;
signal count2: integer:=15;
signal count3: integer:=106;
signal count4: integer:=470;
signal count5: integer:=1471;
signal count6: integer:=3473;
signal count7: integer:=6476;
signal count8: integer:=9908;
signal count9: integer:=12911;
signal count10: integer:=14913;
signal count11: integer:=15914;
signal count12: integer:=16278;
signal count13: integer:=16369;
signal cam_addr_combo : std_logic_vector(13 downto 0);
signal extracted_value: std_logic_vector(3 downto 0);
--array decralation--
subtype elem is std_logic_vector(13 downto 0);
type bit_array is array (0 to 16383) of elem;
signal arr : bit_array;
---------------------
component existingPEX
port
(
a: in std_logic_vector(13 downto 0);
s: out std_logic_vector(3 downto 0) );
end component;
begin
A1 : existingPEX port map(a=>data,s=>extracted_value);
process (extracted_value) begin
if (RorW='0') then
case extracted_value is
when "0000" =>
arr(0)<=data;
when "0001" =>
arr(count1)<=data;
count1 <= count1+1;
when "0010" =>
arr(count2)<=data;
count2 <= count2+1;
when "0011" =>
arr(count3)<=data;
count3 <= count3+1;
when"0100" =>
arr(count4)<=data;
count4 <= count4+1;
when "0101" =>
arr(count5)<=data;
count5 <= count5+1;
when "0110" =>
arr(count6)<=data;
count6 <= count6+1;
when "0111" =>
arr(count7)<=data;
count7 <= count7+1;
when "1000" =>
arr(count8)<=data;
count8 <= count8+1;
when "1001" =>
arr(count9)<=data;
count9 <= count9+1;
when "1010" =>
arr(count10)<=data;
count10 <= count10+1;
when "1011" =>
arr(count11)<=data;
count11 <= count11+1;
when "1100" =>
arr(count12)<=data;
count12 <= count12+1;
when "1101" =>
arr(count13)<=data;
count13 <= count13+1;
when "1110" =>
arr(16383)<=data;
when others =>
null;
end case;
end if;
end process;
process (extracted_value) begin
if (RorW='1') then
case extracted_value is
when "0000" =>
adrs<=data;
when "0001" =>
for i in 1 to 14 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "0010" =>
for i in 15 to 105 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "0011" =>
for i in 106 to 469 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "0100" =>
for i in 470 to 1470 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "0101" =>
for i in 1471 to 3472 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "0110" =>
for i in 3473 to 6475 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "0111" =>
for i in 6476 to 9907 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1000" =>
for i in 9908 to 12910 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1001" =>
for i in 12911 to 14912 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1010" =>
for i in 14913 to 15913 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1011" =>
for i in 15914 to 16277 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1100" =>
for i in 16278 to 16368 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1101" =>
for i in 16369 to 16383 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1110" =>
adrs<=data;
when others =>
null;
end case;
end if;
end process;
end architecture;
PLZ HELP ME...
mistake could be at process statement
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port(
a,b,c: in std_logic;
s,cy: out std_logic);
end entity;
architecture fa of fulladder is
signal d,e,f,g: std_logic;
begin
d<=a xor b;
s<=d xor c;
e<=a and b;
f<=a and c;
g<=b and c;
cy<=e or f or g;
end architecture;
-----------------------------------------------------------------------------------------------
--THIS ONE COUNTS TOTAL NUMDER OR 1'S IN 14 BIT VECTOR a..
library ieee;
use ieee.std_logic_1164.all;
entity existingPEX is
port(
a:in std_logic_vector(13 downto 0); --14 bit input data
s: out std_logic_vector(3 downto 0) ); --4 bit extracted value
end entity;
architecture ar of existingPEX is
signal cs,ss :std_logic_vector(16 downto 1);
component fulladder
port(
a,b,c :in std_logic;
s,cy
ut std_logic);end component;
begin
ss(16)<='0';
ss(14)<='0';
ss(10)<='0';
A1: fulladder port map(a=>a(1),b=>a(2),c=>a(0),s=>ss(1),cy=>cs(1));
A2: fulladder port map(a=>a(4),b=>a(5),c=>a(3),s=>ss(2),cy=>cs(2));
A3: fulladder port map(a=>a(7),b=>a(8 ),c=>a(6),s=>ss(3),cy=>cs(3));
A4: fulladder port map(a=>a(10),b=>a(11),c=>a(9),s=>ss(4),cy=>cs(4));
A5: fulladder port map(a=>a(13),b=>'0',c=>a(12),s=>ss(5),cy=>cs(5));
A6: fulladder port map(a=>ss(2),b=>ss(3),c=>ss(1),s=>ss(6),cy=>cs(6));
A7: fulladder port map(a=>ss(5),b=>'0',c=>ss(4),s=>ss(7),cy=>cs(7));
A8: fulladder port map(a=>cs(1),b=>cs(2),c=>'0',s=>ss(8 ),cy=>cs(8 ));
A9: fulladder port map(a=>cs(4),b=>cs(5),c=>cs(3),s=>ss(9),cy=>cs(9));
A10: fulladder port map(a=>ss(7),b=>'0',c=>ss(6),s=>s(0),cy=>cs(10));
A11: fulladder port map(a=>cs(6),b=>cs(7),c=>'0',s=>ss(11),cy=>cs(11));
A12: fulladder port map(a=>ss(9),b=>'0',c=>ss(8 ),s=>ss(12),cy=>cs(12));
A13: fulladder port map(a=>cs(8 ),b=>cs(9),c=>'0',s=>ss(13),cy=>cs(13));
A14: fulladder port map(a=>ss(12),b=>ss(11),c=>cs(10),s=>s(1),cy=>cs(14));
A15: fulladder port map(a=>ss(13),b=>cs(12),c=>cs(11),s=>ss(15),cy=>cs(15));
A16: fulladder port map(a=>cs(14),b=>ss(15),c=>'0',s=>s(2),cy=>cs(16));
s(3)<=cs(13) or cs(15) or cs(16);
end architecture;
-----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cam_ones_count is
port (
RorW : in std_logic; --read or write--
data : in std_logic_vector(13 downto 0); --input data--
adrs : out std_logic_vector(13 downto 0); --output data--
PorA : out std_logic); -- searched data present or apsent
end entity;
architecture arc of cam_ones_count is
signal count1: integer:=1;
signal count2: integer:=15;
signal count3: integer:=106;
signal count4: integer:=470;
signal count5: integer:=1471;
signal count6: integer:=3473;
signal count7: integer:=6476;
signal count8: integer:=9908;
signal count9: integer:=12911;
signal count10: integer:=14913;
signal count11: integer:=15914;
signal count12: integer:=16278;
signal count13: integer:=16369;
signal cam_addr_combo : std_logic_vector(13 downto 0);
signal extracted_value: std_logic_vector(3 downto 0);
--array decralation--
subtype elem is std_logic_vector(13 downto 0);
type bit_array is array (0 to 16383) of elem;
signal arr : bit_array;
---------------------
component existingPEX
port
(
a: in std_logic_vector(13 downto 0);
s: out std_logic_vector(3 downto 0) );
end component;
begin
A1 : existingPEX port map(a=>data,s=>extracted_value);
process (extracted_value) begin
if (RorW='0') then
case extracted_value is
when "0000" =>
arr(0)<=data;
when "0001" =>
arr(count1)<=data;
count1 <= count1+1;
when "0010" =>
arr(count2)<=data;
count2 <= count2+1;
when "0011" =>
arr(count3)<=data;
count3 <= count3+1;
when"0100" =>
arr(count4)<=data;
count4 <= count4+1;
when "0101" =>
arr(count5)<=data;
count5 <= count5+1;
when "0110" =>
arr(count6)<=data;
count6 <= count6+1;
when "0111" =>
arr(count7)<=data;
count7 <= count7+1;
when "1000" =>
arr(count8)<=data;
count8 <= count8+1;
when "1001" =>
arr(count9)<=data;
count9 <= count9+1;
when "1010" =>
arr(count10)<=data;
count10 <= count10+1;
when "1011" =>
arr(count11)<=data;
count11 <= count11+1;
when "1100" =>
arr(count12)<=data;
count12 <= count12+1;
when "1101" =>
arr(count13)<=data;
count13 <= count13+1;
when "1110" =>
arr(16383)<=data;
when others =>
null;
end case;
end if;
end process;
process (extracted_value) begin
if (RorW='1') then
case extracted_value is
when "0000" =>
adrs<=data;
when "0001" =>
for i in 1 to 14 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "0010" =>
for i in 15 to 105 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "0011" =>
for i in 106 to 469 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "0100" =>
for i in 470 to 1470 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "0101" =>
for i in 1471 to 3472 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "0110" =>
for i in 3473 to 6475 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "0111" =>
for i in 6476 to 9907 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1000" =>
for i in 9908 to 12910 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1001" =>
for i in 12911 to 14912 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1010" =>
for i in 14913 to 15913 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1011" =>
for i in 15914 to 16277 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1100" =>
for i in 16278 to 16368 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1101" =>
for i in 16369 to 16383 loop
cam_addr_combo <= conv_std_logic_vector(i, cam_addr_combo'length);
if (data = arr(i)) then
adrs<= cam_addr_combo;
PorA<='1';
exit;
else
PorA<='0';
end if;
end loop;
when "1110" =>
adrs<=data;
when others =>
null;
end case;
end if;
end process;
end architecture;