HDE
Newbie level 2
Hi everyone,
I have a question in regard to a vhdl package I have created. Hereafter, is the code that works fine:
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE ieee.math_real.log2;
USE ieee.math_real.ceil;
package PKG_globalConstants is
constant Width : integer := 7;
constant FaultyChannels : integer := 3;
constant clockPeriod : INTEGER := 20;
constant pwmPeriod : INTEGER := 320000;
constant dcIintegral : positive := 22;
constant cntWidth : INTEGER := INTEGER(CEIL(LOG2(REAL(pwmPeriod/clockPeriod))))
type pulseShift_array is array (0 to FaultyChannels) of positive;
constant pulseShift : pulseShift_array := ( (2**cntWidth)/(Width-3), (2**cntWidth)/(Width-2), (2**cntWidth)/(Width-1), (2**cntWidth)/(Width) ); ---(line that I need to replace)
end PKG_globalConstants;
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My question is, is it possible to use the following part of code in order to make pulseShift constant array parametric?
I use Xilinx WEB ise 13.2 and I get a syntax error for the 'loop' example. If what I need to do is possible in VHDL, could you please give me the answer? Thanks in advance.
Hearafter is the code I would like to insert in my package;
----------------------------------------------------------------
constant pulseShift : pulseShift_array;
forLoop: for i in 0 to FaultyChannels generate
pulseShift(i) := (2**cntWidth)/(Width-(FaultyChannels-i));
end generate;
----------------------------------------------------------------
I have a question in regard to a vhdl package I have created. Hereafter, is the code that works fine:
--------------------------------------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE ieee.math_real.log2;
USE ieee.math_real.ceil;
package PKG_globalConstants is
constant Width : integer := 7;
constant FaultyChannels : integer := 3;
constant clockPeriod : INTEGER := 20;
constant pwmPeriod : INTEGER := 320000;
constant dcIintegral : positive := 22;
constant cntWidth : INTEGER := INTEGER(CEIL(LOG2(REAL(pwmPeriod/clockPeriod))))
type pulseShift_array is array (0 to FaultyChannels) of positive;
constant pulseShift : pulseShift_array := ( (2**cntWidth)/(Width-3), (2**cntWidth)/(Width-2), (2**cntWidth)/(Width-1), (2**cntWidth)/(Width) ); ---(line that I need to replace)
end PKG_globalConstants;
--------------------------------------------------------------------------------------------------------------------------------------------------
My question is, is it possible to use the following part of code in order to make pulseShift constant array parametric?
I use Xilinx WEB ise 13.2 and I get a syntax error for the 'loop' example. If what I need to do is possible in VHDL, could you please give me the answer? Thanks in advance.
Hearafter is the code I would like to insert in my package;
----------------------------------------------------------------
constant pulseShift : pulseShift_array;
forLoop: for i in 0 to FaultyChannels generate
pulseShift(i) := (2**cntWidth)/(Width-(FaultyChannels-i));
end generate;
----------------------------------------------------------------