VHDL or Verilog as TB for Gate Level Simulation

[sythe]

Many years ago some one told me that it is better to have a verilog/SV testbench for GLS rather than VHDL.
Can some one please explain me why ?

best regards

Simon

 

[ThisIsNotSam]

vhdl is a defunct language, only kept alive because of some FPGA legacy. verilog has evolved a lot, and systemverilog has a lot of verification constructs that help building good testbenches.

it has nothing to do with gate level, both languages can be used to build testbenches. it's about what the languages offer.