brunokasimin
Member level 4
vhdl import
I have synthesize vhdl codes and netlist is generated.now i want to import the vhdl(after optimization) of the netlist from cadence so that i start with my physical design. But somehow there was a problem with import and i received an error when i was importing.
the error is:
duluth: *F,24: logical library name STD must be mapped to a design library [11.2]
can anyone help me??
i have been troubleshooting this error but cannot find the solution.
thanks very much.
I have synthesize vhdl codes and netlist is generated.now i want to import the vhdl(after optimization) of the netlist from cadence so that i start with my physical design. But somehow there was a problem with import and i received an error when i was importing.
the error is:
duluth: *F,24: logical library name STD must be mapped to a design library [11.2]
can anyone help me??
i have been troubleshooting this error but cannot find the solution.
thanks very much.