VHDL Generate loop index

[vlsi_freak]

Hi,

I am working on an HDL for an Altera design. I came a situation where i want to increment vhdl generate loop index by 2.

An example is show below,

LABEL: for i in 1 to CNTR_WIDTH -1 generate

REG1(i) <= ORG_REG(i)(1 downto 0);
REG1(i+1) <= ORG_REG(i)(3 downto 2);

end generate;

I want the generate loop i variable index proceeds like 0,2,4,6 upto the defined range.
Please help me how to do this in vhdl?

Regards,
freak

 

[jducluzeau]

Generate loop describe some identical hardware then this is no sense to have index 0,2,4,6

but you can simply try :

LABEL: for i in 1 to CNTR_WIDTH -1 generate

REG1(2*i) <= ORG_REG(i)(1 downto 0);
REG1(2*i+1) <= ORG_REG(i)(3 downto 2);

end generate;

Regards
Jerome