vhdl basics on range keyword

[royalreddy]

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Code VHDL - [expand]
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constant some_constant : std_ulogic_vector(7 downto 0) := "00111010";
b(some_constant 'range) <= a(some_constant 'range);

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so what is a(some_constant 'range)?

and what is meaning of b(some_constant 'range)?

thanks

 

[K-J]

The 'range attribute returns the 'range' of a vector. In your constant 'some_constant' the range is '7 downto 0'. Using 'range typically can make code easier to reuse since if the bit widths of a vector need to change, then you can often get away with making only one change. For example, let's say you have a std_ulogic_vector signal an unsigned signal and a signed signal that are all somewhat independent but all need to be the same range (whatever that range may be). If you define it like the following: then only one change is needed if the range changes. The other benefit is that it makes it clear to the reader that the various signals are related and must be the same width, not that they are coincidentally the same range.

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Code VHDL - [expand]
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some_sulv: std_ulogic_vector(7 downto 0);
some_uns: unsigned(some_sulv'range);
some_sign: signed(some_sulv'range);

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The meaning of b(some_constant'range) is to take vector b and slice out only the bits that have the same range as 'some_constant'. For example, if b is defined as
b: std_ulogic_vector(15 downto 0);
then b(some_sulv'range) from above is equivalent to b(7 downto 0);

Kevin Jennings

 

[royalreddy]

pcmfcon1 reg arch: 0 to 31 bits, bit 1 OUTFINIT, bit 3 INFINIT, bits 16 to 22 INFTL, bits 24 to 28 OUTFTL and other bits are reserved

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Code VHDL - [expand]
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constant pcmfcon1_OUTFINIT_c : natural                       := 0;
  constant pcmfcon1_INFINIT_c  : natural                       := 1;
  constant pcmfcon1_INFTL_c  : std_ulogic_vector( 8 downto 2)  := "1111111";
  constant pcmfcon1_OUTFTL_c : std_ulogic_vector(13 downto 9)  := "11111";
 
 fcon_outf_tl_o(0) <= CONV_INTEGER(unsigned(pcmfcon(0)(pcmfcon1_OUTFTL_c'range)));

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my question is "pcmfcon1_OUTFTL_c'range" will return pcmfcon(0)(13downto 9) or pcmfcon(0)(24downto 28)?

as per above it should return 13 downto 0, but I am expecting 24 downto 0. whch is correct?

 

[K-J]

pcmfcon1 reg arch: 0 to 31 bits, bit 1 OUTFINIT, bit 3 INFINIT, bits 16 to 22 INFTL, bits 24 to 28 OUTFTL and other bits are reserved

Without any VHDL code, it's not clear what this is supposed to mean other than maybe that's what you're trying to implement or something.

constant pcmfcon1_OUTFINIT_c : natural := 0;
constant pcmfcon1_INFINIT_c : natural := 1;
constant pcmfcon1_INFTL_c : std_ulogic_vector( 8 downto 2) := "1111111";
constant pcmfcon1_OUTFTL_c : std_ulogic_vector(13 downto 9) := "11111";

So the range of pcmfcon1_OUTFTL_c = pcmfcon1_OUTFTL_c'range = 13 downto 9

fcon_outf_tl_o(0) <= CONV_INTEGER(unsigned(pcmfcon(0)(pcmfcon1_OUTFTL_c'range)));

my question is "pcmfcon1_OUTFTL_c'range" will return pcmfcon(0)(13downto 9) or pcmfcon(0)(24downto 28)?

Not sure what pcmfcon(0) is but since pcmfcon1_OUTFTL_c'range = 13 downto 9 then
fcon_outf_tl_o(0) <= CONV_INTEGER(unsigned(pcmfcon(0)(pcmfcon1_OUTFTL_c'range)));
becomes
fcon_outf_tl_o(0) <= CONV_INTEGER(unsigned(pcmfcon(0)(13 downto 9)));

as per above it should return 13 downto 0, but I am expecting 24 downto 0. whch is correct?

Not sure where you got either of these two.

I'm guessing though that you're trying to define the bits in a 32 bit record. If you are, then here is how I do it:

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Code VHDL - [expand]
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type t_MY_REGS is record
    Reserved1:   std_ulogic_vector(0 downto 0);
    OUTFINIT:    std_ulogic_vector(1 downto 1);
    Reserved2:   std_ulogic_vector(2 downto 2);
    INFINIT:       std_ulogic_vector(3 downto 3);
    Reserved2:   std_ulogic_vector(15 downto 4);
    INFTL:         std_ulogic_vector(22 downto 16);
    OUTFTL:      std_ulogic_vector(28 downto 24);
    Reserved2:   std_ulogic_vector(31 downto 29);
end record t_MY_REGS;
type arr_t_MY_REGS is array(natural range <>) of t_MY_REGS;  -- In case you need an array of these...looked like you did
 
signal pcmfcon1: t_MY_REGS;

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This way you don't have a ton of constants that then get used to define the bit fields and then get used in the code for other purposes. Where the code needs to know about the size of something it simply uses the array attributes. For example:

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Code VHDL - [expand]
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pcmfcon1.OUTFTL <= std_ulogic_vector(to_unsigned(5, pcmfcon1.OUTFTL'length));

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Kevin Jennings

 

[royalreddy]

I mean 24 to 28 not 24 downto 0

 

[xtcx]

I wonder why you expect (24 to 28)?
Also I wonder why you expect pcmfcon1_OUTFTL_c'range will return pcmfcon(0)(24 to 28)?...
By nature, it should take (13 downto 9), that is (4 downto 0); because you have declared
constant pcmfcon1_OUTFTL_c : std_ulogic_vector(13 downto 9) := "11111";
which is a 5 bit SLV

Can you post your code?.

 

[royalreddy]

bcz in OUFTL field I have my 'out fifo trigger level', so I am expecting that should return

you can see code in my 2nd post

what is the vector pattern of this statement? constant pcmfcon1_INFTL_c : std_ulogic_vector( 8 downto 2) := "1111111";
what will it return for pcmfcon1_INFTL_c(3 downto 0)?

 

[K-J]

what is the vector pattern of this statement? constant pcmfcon1_INFTL_c : std_ulogic_vector( 8 downto 2) := "1111111";

What do you mean by a 'vector pattern of this statement'?

what will it return for pcmfcon1_INFTL_c(3 downto 0)?

An error will be returned because '3 downto 0' is outside of the range '8 downto 2' which is the range that is defined for pcmfcon1_INFTL_c.

Do you have access to a compiler? If so, you should use it, you'll get answers much quicker.

Kevin Jennings

 

[royalreddy]

width of pcmfcon1_INFTL_c ?

and why we declare pcmfcon1_INFTL_c : std_ulogic_vector( 8 downto 2) := "1111111"; instead of pcmfcon1_INFTL_c : std_ulogic_vector( 6 downto 0) := "1111111";
is there any purpose behind this?

 

[K-J]

width of pcmfcon1_INFTL_c ?

The width of any vector is available as an attribute of that vector. In this case, pcmfcon1_INFTL_c'length.

and why we declare pcmfcon1_INFTL_c : std_ulogic_vector( 8 downto 2) := "1111111"; instead of pcmfcon1_INFTL_c : std_ulogic_vector( 6 downto 0) := "1111111";
is there any purpose behind this?

There might be, but without seeing everything that you're looking at I don't know what was intended by the original designer. The short answer to your question is 'Maybe'.

As I mentioned in my earlier post where I showed how I would go about defining a record for a collection of bits that is intended to be part of some 32 bit register of some sort (possibly because this has a software interface to somebody else), I used the intended bit positions right in the record definition. This does a couple of things:
- Clearly specifies which fields correspond to particular bit positions in the record. To somebody else not necesarilly familiar with the design it is immediately clear what function is performed by each bit. Presumably there is then a specification that defines what that function actually performs, but that is outside the scope of this discussion
- Makes for a rapid and nearly automated way to create functions that convert between a generic std_ulogic_vector and the record.
- Changes to bit positions of fields can be done by editing the record definition and recompiling. No other edits necessary.

There really shouldn't be a need to refer to specific bits within a field of a record. If you find you're doing that, then you likely don't have the right record definition to start with. Fix that instead. As an example, from that earlier post was a field defined within the record as:

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Code VHDL - [expand]
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INFTL:         std_ulogic_vector(22 downto 16);

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If you find yourself wanting to refer to the most (or least) significant bit of xx.intfl, ask yourself why? The purpose of defining the record is so that elements within the record are rather atomic; you assign to or compare things with the whole field like this:

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Code VHDL - [expand]
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xx.intfl <= "1010101";
  xx.intfl <= std_ulogic_vector(to_unsigned(5, xx.intfl'length);
  if (to_integer(unsigned(xx.intfl)) = 19) then

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So why do you care that the bits that make up xx.intfl are bits 16 thru 22?

Kevin Jennings