Very strange bug with Xilinx

[asjohnas]

There is a big problem with determining the cause very strange bug:
Project in the crystal Xilinx works fine, but from only 7-10 hours and then one part of it hangs.

Now the details: By many experiments revealed that error inside the trigger of Xilinx chip (ie the output signal ceases to be):
start_flag <= (((EQUAL (rxd_sync (63 downto 56), SFD))
and (not rxc_sync (7)))
or preserve_preamble) and start_code_found and enable;

Start_flag signal stops working. When I push reset to the block, and consequently on the trigger which is formed according to the condition does not lead to the conclusion of this "hung" state.
And even after it happened a strange crash, I am use chipscope contemplate the presence of all the right signals are present in the subject.

Tested:
1. Qualitativeness layout signal FPGAEditor
2. Constraints
3. Core supply voltage
4. The presence of reset and their timing for all signals (reset logon to all signals is separately verified)
5. Bug is not related to the work which lies near the equipment as shown on circuit boards located in other parts of the firm.
6. Without the cooler crystal is heated to 71 degrees, but warmed more specifically - to cause a glitch faster 6-hours and could not

Generate a tremendous request for more different versions because of what this could be!

 

[vipinlal]

Is this a problem with any register overflow or something like that?

You may have a register declared in your program which keeps on counting. Under normal running time (may be less than 1 or 2hrs) this register may not get overflowed but when the running is high enough then this gets overflowed and the whole logic fails.Did you think in that direction? Just noting down my points which came to my mind...

--vipin
VHDL coding tips and tricks

 

[permute]

Are any of the inputs asynchronous to the clock domain where start_flag is used? Further, is start_flag used in more than one clock domain? Are you certain all signals do what you think they do?

sim can have issues in that basic sims will not fail due to skew, while real designs will. Likewise, the sim might not provide full coverage of test cases.

 

[asjohnas]

No I not have any counters that can overflowed. I am tested whole my design for find this. If I have counters it is overflowed very more time in one minute.
I not said that frequncy about 150MHz. But chip very quick (-3)

All signals in one clock domain. I am not describe situation in simulation mode. It is real hard test. In this real test my project work 10 hours without errors but after all it fail - and reset can't help! This is main strange thing!