asjohnas
Junior Member level 3
There is a big problem with determining the cause very strange bug:
Project in the crystal Xilinx works fine, but from only 7-10 hours and then one part of it hangs.
Now the details: By many experiments revealed that error inside the trigger of Xilinx chip (ie the output signal ceases to be):
start_flag <= (((EQUAL (rxd_sync (63 downto 56), SFD))
and (not rxc_sync (7)))
or preserve_preamble) and start_code_found and enable;
Start_flag signal stops working. When I push reset to the block, and consequently on the trigger which is formed according to the condition does not lead to the conclusion of this "hung" state.
And even after it happened a strange crash, I am use chipscope contemplate the presence of all the right signals are present in the subject.
Tested:
1. Qualitativeness layout signal FPGAEditor
2. Constraints
3. Core supply voltage
4. The presence of reset and their timing for all signals (reset logon to all signals is separately verified)
5. Bug is not related to the work which lies near the equipment as shown on circuit boards located in other parts of the firm.
6. Without the cooler crystal is heated to 71 degrees, but warmed more specifically - to cause a glitch faster 6-hours and could not
Generate a tremendous request for more different versions because of what this could be!
Project in the crystal Xilinx works fine, but from only 7-10 hours and then one part of it hangs.
Now the details: By many experiments revealed that error inside the trigger of Xilinx chip (ie the output signal ceases to be):
start_flag <= (((EQUAL (rxd_sync (63 downto 56), SFD))
and (not rxc_sync (7)))
or preserve_preamble) and start_code_found and enable;
Start_flag signal stops working. When I push reset to the block, and consequently on the trigger which is formed according to the condition does not lead to the conclusion of this "hung" state.
And even after it happened a strange crash, I am use chipscope contemplate the presence of all the right signals are present in the subject.
Tested:
1. Qualitativeness layout signal FPGAEditor
2. Constraints
3. Core supply voltage
4. The presence of reset and their timing for all signals (reset logon to all signals is separately verified)
5. Bug is not related to the work which lies near the equipment as shown on circuit boards located in other parts of the firm.
6. Without the cooler crystal is heated to 71 degrees, but warmed more specifically - to cause a glitch faster 6-hours and could not
Generate a tremendous request for more different versions because of what this could be!