Very Low Jitter PLL Design

[chanchg]

Hello,

I have been assigned a task to do a competitive study on very low jitter PLL's. The PLL has tight specs of 25ps peak-to-peak jitter in 0.13u digital CMOS process.

1)How feasible is it? If I use ring-oscillator based VCO, can I meet these specs? How much we can achieve by using a separate voltage regulator for this VCO?

2) If I use LC based VCO, can I achieve these specs? The inductor layout in LC based oscillator in most of the 0.13u process becomes challenging coz of lack of top-thick metal to achieve high Q factor... So is there any other solution?

I hope my query can be answered..

Best,
Chanchg

 

[psheldon]

I have been tasked also to do a low jitter PLL in 130nm. You can't quite get there with a Ring VCO unless you burn tens of mA in VCO current. You will probably need a spiral inductor osc with thick top layer metal.

 

[love_analog]

This one is not too bad. you can do RO. Just make sure you make it rail to rail swing, use min # of stages (if doing single ended) and put a regulator on the Vcc.

This is something like 2-2.4ps rms depending upon your BER requirment