choodzik
Newbie level 6
hello everybody
My name is Peter and i am a student. My engineer degree subject is to compare and design few architectures of voltage comparators. Which of them takes less current works faster etc.
these are the needs of the comparator:
- voltage offset less then 5mv
- frequency 50khz - 2 Mhz
- very low current consumption ( comparator should take single mikro-ampers )
- maksimum time for the output answer is the 25% of clock frequency
- comparator should be loaded with 100fF capacitance
I would like to ask you about some papers and help for me. Maybe you have similar problem in the past or you designed some comparators.
Another thing is that i designed a open loop comparator. It is preety fast and takes only 1 uA. But the problem is that i only cannot take normal clock signal ( i mean high and low voltage level of clock signal is 50% of period so k=1/2 )
In my design i use not normal clock signal
for ex. high level is 0.06 us when period is 0.5 us
So my question is how to design some circuit which will divide me the frequency of the clock. I just want to make clock signal with the frequency from 50 khz - 2 Mhz
but the high level will be about 10% of period not 50% as it is usual. I know there are some frequency dividers etc. but i takes usually much current consumption so i cannot use it in my uA comparator.
Another question is how to measure voltage offset of the comparator in the hspice??
I am new on this forum so i don't have any points allready but i would apreciate for every help and papers from you. my mail p_bejm@o2.pl
thanks in advance
My name is Peter and i am a student. My engineer degree subject is to compare and design few architectures of voltage comparators. Which of them takes less current works faster etc.
these are the needs of the comparator:
- voltage offset less then 5mv
- frequency 50khz - 2 Mhz
- very low current consumption ( comparator should take single mikro-ampers )
- maksimum time for the output answer is the 25% of clock frequency
- comparator should be loaded with 100fF capacitance
I would like to ask you about some papers and help for me. Maybe you have similar problem in the past or you designed some comparators.
Another thing is that i designed a open loop comparator. It is preety fast and takes only 1 uA. But the problem is that i only cannot take normal clock signal ( i mean high and low voltage level of clock signal is 50% of period so k=1/2 )
In my design i use not normal clock signal
for ex. high level is 0.06 us when period is 0.5 us
So my question is how to design some circuit which will divide me the frequency of the clock. I just want to make clock signal with the frequency from 50 khz - 2 Mhz
but the high level will be about 10% of period not 50% as it is usual. I know there are some frequency dividers etc. but i takes usually much current consumption so i cannot use it in my uA comparator.
Another question is how to measure voltage offset of the comparator in the hspice??
I am new on this forum so i don't have any points allready but i would apreciate for every help and papers from you. my mail p_bejm@o2.pl
thanks in advance