wuting26
Newbie level 2
I have posted this in Elementary forum, but thought that it's more relevant to here --
I would like to do verification on a mixed-signal design, but have a problem when netlisting functional views. Look forward to kind help and replies. Thanks in advance.
I have written functional views for analog blocks and tried Verilog XL. In Verilog Netlisting Options, I have put "behavioral functional schematic symbol" in order in "Netlist These Views". I have also put "behavioral functional symbol" in order in "Stop Netlisting at Views". I expect it run netlisting in hierachy, and search for functional first rather than schematic. When it netlist a functional view, it should stop searching in lower level of this cell. However, Verilog XL gave me all schematic views from top to bottom. It does not netlist functional view at all, and therefore, not stopping at the levels I want.
Any suggestions?
BTW, when I wrote functional verilog code, it gave me error message " cannot find ncvlog executable from your path". I thought this has no impact on my netlisting using Verilog XL.
Hope you can help me out! Thank you.
I would like to do verification on a mixed-signal design, but have a problem when netlisting functional views. Look forward to kind help and replies. Thanks in advance.
I have written functional views for analog blocks and tried Verilog XL. In Verilog Netlisting Options, I have put "behavioral functional schematic symbol" in order in "Netlist These Views". I have also put "behavioral functional symbol" in order in "Stop Netlisting at Views". I expect it run netlisting in hierachy, and search for functional first rather than schematic. When it netlist a functional view, it should stop searching in lower level of this cell. However, Verilog XL gave me all schematic views from top to bottom. It does not netlist functional view at all, and therefore, not stopping at the levels I want.
Any suggestions?
BTW, when I wrote functional verilog code, it gave me error message " cannot find ncvlog executable from your path". I thought this has no impact on my netlisting using Verilog XL.
Hope you can help me out! Thank you.