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verilog .V file errors "Verilog HDL Implicit Net warning"

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bteddy1

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File is attached.
What is wrong?
How do I fix it?

Error:
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(45): created implicit net for "G14"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(49): created implicit net for "G24"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(49): created implicit net for "Q12"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(62): created implicit net for "G16"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(62): created implicit net for "Q02"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(63): created implicit net for "Q03"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(64): created implicit net for "Q04"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(65): created implicit net for "Q05"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(68): created implicit net for "G13"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(68): created implicit net for "G15"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(69): created implicit net for "G18"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(71): created implicit net for "G12"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(73): created implicit net for "G11"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(77): created implicit net for "G17"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(83): created implicit net for "G00"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(83): created implicit net for "G05"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(83): created implicit net for "Q00"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(84): created implicit net for "G10"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(84): created implicit net for "Q01"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(86): created implicit net for "G100"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(87): created implicit net for "G101"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(88): created implicit net for "G102"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(89): created implicit net for "G103"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(90): created implicit net for "G104"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(91): created implicit net for "G105"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(92): created implicit net for "G106"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(93): created implicit net for "G107"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(94): created implicit net for "G108"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(95): created implicit net for "G109"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(98): created implicit net for "G110"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(99): created implicit net for "G111"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(100): created implicit net for "G112"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(101): created implicit net for "G113"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(102): created implicit net for "G114"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(103): created implicit net for "G115"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(104): created implicit net for "G116"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(105): created implicit net for "G117"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(106): created implicit net for "G118"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(107): created implicit net for "G119"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(120): created implicit net for "G20"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(120): created implicit net for "G19"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(122): created implicit net for "G21"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(122): created implicit net for "Q10"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(130): created implicit net for "G22"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(130): created implicit net for "G19B"
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(132): created implicit net for "G23"
Click to expand...

Code: 
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    23:27:41 05/06/2011
// Design Name:
// Module Name:    stepper
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

//comment out next line if slow decay is desired
`define fastdecay

//////////////////////////////////////////////////////////////////////////////////
//
// Module Name: DRV_10uS
//
//////////////////////////////////////////////////////////////////////////////////
module DRV_10uSTP
(  input CLK, AIN, BIN, DIR, STP, OSCA, RES,
    inout STBY,
    output ASIN, BSIN, DUMP, A0, A1, B0, B1, OSCB
    ,output w1,w2   //for debug
   ,output [7:0] q //for debug
);  

    wire [3:0] QA;   //step counter, 4 bits for 10 steps
   
    wire [7:0] QB;  //sin-cos PWM counter
    wire [1:0] QC;
    wire [2:0] QD;
   
    //T_BASE--------------------------------------------------------------------------
   CB8R C03 (.C(CLK), .R(G14), .Q(QB));
 
    //Slope compensation
`ifdef fastdecay  
    DF F12 (.C(CLK), .D(G24), .R(1'b0), .CE(1'b1), .S(1'b0), .Q(Q12));  //always slope comp, for fast decay mode
`else
    DF F12 (.C(CLK), .D(G24), .R(1'b0), .CE(1'b1), .S(~STBY), .Q(Q12));  //slope comp only during stby, for recir mode
`endif


    assign DUMP = (Q12 | STBY )? 1'b0 : 1'bz;  //no comp during stdby.  Keep dump grounded during stdby to avoid hi voltage
    assign G24 = QB[7] & QB[6] & QB[5] & QB[4];

    assign OSCB = ~OSCA;
   
 
    //PH_GEN--------------------------------------------------------------------------
    DF F02 (.C(CLK), .D(DIR), .R(1'b0), .S(1'b0), .CE(G16),  .Q(Q02));
    DF F03 (.C(CLK), .D(STP), .R(1'b0), .S(1'b0), .CE(1'b1), .Q(Q03));
    DF F04 (.C(CLK), .D(Q03), .R(1'b0), .S(1'b0), .CE(1'b1), .Q(Q04));
    DF F05 (.C(CLK), .D(G16), .R(1'b0), .S(1'b0), .CE(1'b1), .Q(Q05));
 
    CB2BRE C00 (.C(CLK), .UD(Q02), .R(~RES), .CE(G14), .Q(QC));
    CB4BRE C01 (.C(CLK), .UD(G13), .R(~RES), .CE(G15), .Q(QA));
    CB3RE C02 (.C(CLK), .R(Q05), .CE(G18), .Q(QD));

    assign G12 = QC[1] ^ QC[0];
    assign G13 = QC[0] ^ Q02;  
    assign G11 = (G13 & QA[3] & QA[0])  |   (~G13 & ~QA[3] & ~QA[2] & ~QA[1] & ~QA[0]);
       assign G14 = G11 & Q05;
    assign G15 = ~G11 & Q05;
    assign G16 = Q03 & ~Q04;
    assign G17 = QD[2] & QD[1] & QD[0];
    assign STBY = G17 ? 1'bz : 1'b0;  
    assign G18 = ~G17 & QB[7] & QB[6] & QB[5] & QB[4] & QB[3] &QB[2] & QB[1] & QB[0];
 
   
    //ASIN_COS 10 steps -------------------------------------------------------------------------
    DF F00 (.C(CLK), .D(G00), .R(G05), .S(1'b0), .CE(1'b1), .Q(Q00));
    DF F01 (.C(CLK), .D(G10), .R(G05), .S(1'b0), .CE(1'b1), .Q(Q01));
   
    assign G100 = QA[3]&~QA[2]&~QA[1]& QA[0]&QB[7]& QB[6]&QB[5]&QB[4]&QB[3]&QB[2]&QB[1];
    assign G101 = QA[3]&~QA[2]&~QA[1]&~QA[0]&QB[7]& QB[6]&QB[5]&QB[4]&QB[3];  
    assign G102 =~QA[3]& QA[2]& QA[1]& QA[0]&QB[7]& QB[6]&QB[5]&QB[3]&QB[2];
    assign G103 =~QA[3]& QA[2]& QA[1]&~QA[0]&QB[7]& QB[6]&QB[4]&QB[3]&QB[0];
    assign G104 =~QA[3]& QA[2]&~QA[1]& QA[0]&QB[7]& QB[6]&QB[1]&QB[0];  
    assign G105 =~QA[3]& QA[2]&~QA[1]&~QA[0]&QB[7]& QB[5]&QB[2]&QB[1];
    assign G106 =~QA[3]&~QA[2]& QA[1]& QA[0]&QB[7]& QB[2]&QB[0];
    assign G107 =~QA[3]&~QA[2]& QA[1]&~QA[0]&QB[6]&QB[5]&QB[1];  
    assign G108 =~QA[3]&~QA[2]&~QA[1]& QA[0]&QB[5]&QB[4]&QB[3]&QB[2];
    assign G109 =~QA[3]&~QA[2]&~QA[1]&~QA[0]&QB[4]& QB[2];
                                                                                                                                         
    //BSIN_COS 10 steps -------------------------------------------------------------------------
    assign G110 =~QA[3]&~QA[2]&~QA[1]&~QA[0]&QB[7]& QB[6]&QB[5]&QB[4]& QB[3]&QB[2]&QB[1];  
    assign G111 =~QA[3]&~QA[2]&~QA[1]& QA[0]&QB[7]& QB[6]&QB[5]&QB[4]& QB[3];
    assign G112 =~QA[3]&~QA[2]& QA[1]&~QA[0]&QB[7]& QB[6]&QB[5]&QB[3]&QB[2];
    assign G113 =~QA[3]&~QA[2]& QA[1]& QA[0]&QB[7]& QB[6]&QB[4]&QB[3]&QB[0];
    assign G114 =~QA[3]& QA[2]&~QA[1]&~QA[0]&QB[7]& QB[6]&QB[1]&QB[0];
    assign G115 =~QA[3]& QA[2]&~QA[1]& QA[0]&QB[7]&QB[5]&QB[2]&QB[1];
    assign G116 =~QA[3]& QA[2]& QA[1]&~QA[0]&QB[7]& QB[2]&QB[0];
    assign G117 =~QA[3]& QA[2]& QA[1]& QA[0]&QB[6]&QB[5]&QB[1];
    assign G118 = QA[3]&~QA[2]&~QA[1]&~QA[0]&QB[5]&QB[4]&QB[3]&QB[2];
    assign G119 = QA[3]&~QA[2]&~QA[1]& QA[0]&QB[4]& QB[2];

    assign G00 = Q00 | G100 | G101 | G102 | G103 | G104 | G105 | G106 | G107 | G108 | G109;  //asin
    assign G10 = Q01 | G110 | G111 | G112 | G113 | G114 | G115 | G116 | G117 | G118 | G119;  //bsin
   
    assign G05 = ~QB[7] & ~QB[6] & ~QB[5] & ~QB[4] & ~QB[3] & ~QB[2] & ~QB[1] & ~QB[0];  
    assign BSIN = ~Q00 ? 1'bz : 1'b0;
    assign ASIN = ~Q01 ? 1'bz : 1'b0;
   
   
    //PH_DRV----------------------------------------
   
    //phase A
    DF F06 (.C(CLK), .D(G20),  .R(G19), .S(1'b0), .CE(1'b1), .Q(A0));
    DF F07 (.C(CLK), .D(~G20), .R(G19), .S(1'b0), .CE(1'b1), .Q(A1));
    DF F10 (.C(CLK), .D(G21),  .R(G24), .S(1'b0), .CE(1'b1), .Q(Q10));
`ifdef fastdecay
   assign G19  = ~RES | (STBY & Q10 & (QB[7] | QB[6]));  //phase A, fast mode decay
`else
   assign G19  = ~RES | (Q10 & (QB[7] | QB[6]));  //phase A, slow mode decay always
`endif

    //phase b
    DF F08 (.C(CLK), .D(G22),  .R(G19B), .S(1'b0), .CE(1'b1), .Q(B0));
    DF F09 (.C(CLK), .D(~G22), .R(G19B), .S(1'b0), .CE(1'b1), .Q(B1));
    DF F11 (.C(CLK), .D(G23),  .R(G24), .S(1'b0), .CE(1'b1), .Q(Q11));
`ifdef fastdecay
   assign G19B = ~RES | (STBY & Q11 & (QB[7] | QB[6]));  //phase B, fast mode decay
`else
   assign G19B = ~RES | (Q11 & (QB[7] | QB[6]));  //phase B, slow mode decay always
`endif

    assign G22 = Q11 ^ QC[1]; //assign G22 = Q11 ^ QD[1];
    assign G23 = Q11 | ~BIN;
    assign G20 = Q10 ^ G12;
    assign G21 = Q10 | ~AIN;


   
    //the rest of the main module code here:
endmodule



/////////////////////////////////////////////////////////////////////////////////-
module DF (input D, C, CE, R, S, output Q);
reg df = 0;
always @(posedge C)
    if (R)
        df <= 1'h0;
    else if (S)
        df <= 1'b1;
    else if (CE)
        df <= D;
    assign Q = df;
endmodule

/////////////////////////////////////////////////////////////////////////////////-
module CB8R (input C, R, output [7:0] Q);
reg [7:0] count = 0;
always @(posedge C)
    if (R)
        count <= 0;
    else
        count <= count + 1;
    assign Q = count;
endmodule

/////////////////////////////////////////////////////////////////////////////////-
module CB2BRE (input UD, R, CE, C, output [1:0] Q);
reg [1:0] u_d = 0;
always @(posedge C)
    if (R)
        u_d <= 0;
    else if (CE)
        if (UD) begin
            u_d <= u_d + 1;
        end
        else begin
            u_d <= u_d - 1;
        end
    assign Q = u_d;
endmodule

//////////////////////////////////////////////my add///////////////////////////////////-
module CB3BRE (input UD, R, CE, C, output [2:0] Q);
reg [2:0] u_d = 0;
always @(posedge C)
    if (R)
        u_d <= 0;
    else if (CE)
        if (UD) begin
            u_d <= u_d + 1;
        end
        else begin
            u_d <= u_d - 1;
        end
    assign Q = u_d;
endmodule


//////////////////////////////////////////////my add///////////////////////////////////-
module CB4BRE (input UD, R, CE, C, output [3:0] Q);
reg [3:0] u_d = 0;
always @(posedge C)
    if (R)
        u_d <= 0;
    else if (CE)
        if (UD) begin
            u_d <= u_d + 1; // if UD is high, count up
        end
        else begin
            u_d <= u_d - 1; //else count down
        end
    assign Q = u_d;
endmodule





////////////////////////////////////////corrected output [7:0]/////////////////////////////////////////-
module CB3RE (input C, R, CE, output [2:0] Q);
reg [2:0] count = 0;
always @(posedge C)
    if (R)
        count <= 0;
    else if (CE)
        count <= count + 1;
    assign Q = count;
endmodule
Warning (10236): Verilog HDL Implicit Net warning at 10ustep_stepperdriver.v(132): created implicit net for "Q11"
 
Last edited by a moderator:

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It is a Warning not Error!
Check if the inputs and outputs are correctly mapped during module instantiation.
 

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You didn't declare any of the internal signals beside QA, QB, QC, and QD.

You should read a Verilog tutorial/book to learn the language syntax and structure.
 

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