Verilog syntax problem

[mediatek]

Q1. X is tri port in module A
Y is tri port in module B
if I set wire Z=X
then A a1 (.X(X));// now X=1
B b1 (.Y(Z));// Z= unknow
but if B b1 (.Y(X));// then Y =1
why?
Q2.
Is there any document mention about verilog syntax
ex.
*weak0, weak1) buf ....................

 

[baonguyenpro]

You find IEEE standard about Verilog
I don't remember exactly the document name now.