wls
Member level 4
Hello . I am writing an timer counter with apb interface (slave) . At each overflow count or input capture signal , a pulse trigger is generated . The interrupt enable register , interrrupt register and clear interrupt register reside at apb slave side ? If the clear register is set (1) , the interrupt is clear and clear is auto clear.
How do i write a verilog rtl to handle simultaneous interrupt signal and clear signal , if both trigger same time . Can anyone give example of rtl code of handling clear interrupt and interrupt simultaneously.
Long time , i didnt write verilog , most forgot.
Appreciate the help .....
REgards.
How do i write a verilog rtl to handle simultaneous interrupt signal and clear signal , if both trigger same time . Can anyone give example of rtl code of handling clear interrupt and interrupt simultaneously.
Long time , i didnt write verilog , most forgot.
Appreciate the help .....
REgards.