verilog race condition on Async Reset

[vipulsinha]

verilog async reset

One reason not to use asynchronous resets is that Verilog cannot model
them without a race condition. Typical async reset flop:

always @ (posedge ck or negedge rst) begin
if (!rst) q <= 0;
else q <= d;
end

What happens when rst is Deasserted at the same time as ck is asserted?
Either ck goes high first, and rst is still low, so q gets zero. Or rst
goes high first, and when ck fires, q gets d

Pls comment

 

[mmarco76]

reset time verilog

In your code rst condition shall prevail because in the "if" clause the first condition is evaluated and if true only that statement will be done.

I'm not very fond on verilog (I use VHDL most of all) but I think it's the same and the always condition only trigger the code under it if it's verified.

 

[sareene]

race condition verilog

Hi,
Even though reset is an asynchronous signal it has to satisfy removal & recovery timing requirements for proper functioning of the flop. The reset signal can be deasserted only after the removal time, otherwise it will result in metastability.
Removal time is the minimum amount of time that an asyn control signal must be stable after the clock active-edge transition,when asyn signal is deasserted
If reset is deasserted at the active edge of the clock, the output of the flop will become unpredictable, it can either latch the data or remain in reset state