Verilog Question about Always sensitivity list

[adamsogood]

Hi,

can anybody explain the "*" in the sensitivity list in the following verilog code. What's that for? thank you.


always @(*) begin
if (!reset) begin
A_r <= 1'bz;
B_r <= 1'bz;
line_en <= 1'b0;
end else begin
if (line_en) begin
A_r <= #Delay_rd B;
B_r <= 1'bz;
end else begin
B_r <= #Delay_g A;
A_r <= 1'bz;
end
end
end

 

[devas]

Hi,

always(*) is Verilog-2001 syntax. It simplifies the sensitivity list. * means be sensitive changes on any values which are read in the following group.

Devas

 

[gmajay123]

Hi. When modelling combinational logic we must make sure all signals that appear on the RHS of any assignment but be present in the sensitivity list, so that, when the signal changes the assignment is executed. Missing any signal in the sensitivity list "may" model a latch. So, to avoid a syntactical error of missing a signal in the list the "*" was added to the language so that all signals present in RHS of all assignments are automatically considered to be present in the sensitivity list.

NOTE: "=" and not "<=" should be used while modelling combinational logic.

If the module you are designing is a sequential logic block i am not sure if you can use the "@*" thing. This is because there is no reserved keyword for clock. The simulator doesn't know the difference between a clock and reset signal. Consider the d flipflop with clock named b and reset named a.

always @ (negedge a or posedge b)
begin
if(!a)
d<=0;
else
d<=q;
end

The signal which is not used in any decision statements is the clock. "a" was used in the if statement and b was not used anywhere, so b is considered as the clock.

This is the reason you cannot use "@*" to model sequential logic.

 

[ljxpjpjljx]

* means any changes of signals in your case list!