verilog PWM, counter not incrementing

[bobobano]

My digital circuitry class was assigned to write the code in verilog for a PWM. Unfortunately I can't even get my code to work.

module PWM (clk,duty,period,B);

input clk,duty,period;
output reg B;
reg [8:0]count=0; //8 bit counter

always @ (negedge clk)
 begin
  if (count<duty)  assign B=1;
  else assign B=0;
  if (count>=period) count = 0; //reset count at end of period
  count = count + 1; //increment counter
  $display("%g",count); //display the current count
 end
endmodule

module testbench();

wire A;
reg clk=0;

always #1 if($time==20) $finish; //stop program after 20 cycles
always #1 clk=!clk; //alternate clock pulse


initial begin
  $monitor ("%b - %b ---- %g",A,clk,$time);
 end

PWM inst (clk,6,10,A); //duty cycle = 60%, period = 10 cycles

endmodule

From what I understand there isn't any reason the counter should not be incrementing, yet it increments to 1, and then stays there.

I am writing using Icarus for windows version 0.9.3 and it gives me no errors on compiling, even my lab teacher doesn't know why it's not working.

Help me Obiwan-Kenobi, you're my only hope.

 

[alexan_e]

Hi

I'm a VHDL guy but i have managed to fix the counting, simulation seems to be working but your duty cycle was not correct, so i have also added an else statement because you were doing count=0 and immediately count=count+1 in the same clock cycle;

module PWM (clk,duty,period,B);

input clk;
input [8:0] duty,period;
output reg B;
reg [8:0] count=0; //8 bit counter

always @ (negedge clk)
 begin
  if (count<duty)  assign B=1;
  else assign B=0;
  if (count>=period) count = 0; //reset count at end of period
  else count = count + 1; //increment counter
  $display("%g",count); //display the current count
 end
endmodule

module testbench();

wire A;
reg clk=0;

always #1 if($time==20) $finish; //stop program after 20 cycles
always #1 clk=!clk; //alternate clock pulse


initial begin
  $monitor ("%b - %b ---- %g",A,clk,$time);
 end

PWM inst (clk,6,10,A); //duty cycle = 60%, period = 10 cycles

endmodule

Alex