verilog parsing error

[Alka Arora]

Hi ,

I am getting following error for this reg.

reg [63:0] data_vec[0:4];
/ Error: PARSE_ERROR: Parsing syntax error
// Multiple words referenced for memory Variable 'data
_vec' near token '('


How can I get rid of this error.How can I declare 5*64 bit vector?


Thanks
Alka

 

[graphene]

try reg [63:0] data_vec[4:0];

---------- Post added at 17:54 ---------- Previous post was at 17:51 ----------

well actually the sequence of this declaration can give us why and how we shall rectify it..

 

[Alka Arora]

Hi,

Thanks.I get same error.I believe I need to make one signal of 5*64 .How Can I do that ?

 

[graphene]

i guess u myt have also tried reg [5*64:0]; else pl try...

---------- Post added at 18:08 ---------- Previous post was at 18:06 ----------

most importantly.. unless I/we can understadn the program or sequence, the solution cannot be given exactly... may b u place the code or the module here for us get an overview...

 

[Alka Arora]

I am getting "error: Multiple words referenced for memory Variable " in both the cases.

 

[graphene]

well i tried all 3 possib. in my program juz now to help u, but my simulator doesnt say anything so... all went well..

 

[Alka Arora]

It should be reg [5*64:0] or [5*63:0] ?

 

[graphene]

sorry not 64 but 63 .....

---------- Post added at 18:54 ---------- Previous post was at 18:35 ----------

Hallo Alka, it shall b great if u can acknowledge by letting us know d result... we also invest time in helping and hence learning... thnku

 

[Alka Arora]

Hi ,

The reg [5*64-1:0] worked.I still have to compare the results.

Thanks