vlsi_freak
Full Member level 2
Verilog Package File
Hi All,
I have some lines of code in my project like,
Caseaddr[7:0]
8'b 00000000 : reg <= '1';
8'b 00000001 : reg <= '0';
-
-
8'b11111111 : reg <= '1'
Here i would like to replace address with some names like ,
Caseaddr[7:0]
Reg1 : reg <= '1';
Reg2 : reg <= '0';
-
-
Regn : reg <= '1'
I have made a file REG_PKG.v and defined like,
'define 8'b 00000000 Reg1
But still compiler is throwing error saying that, Reg1, Reg2 etc is not declared.
Here, i have compiled the Package file and added line `include in my original code.
Please help me, how to make a constants file in Verilog similar to VHDL.
regards,
freak
Hi All,
I have some lines of code in my project like,
Caseaddr[7:0]
8'b 00000000 : reg <= '1';
8'b 00000001 : reg <= '0';
-
-
8'b11111111 : reg <= '1'
Here i would like to replace address with some names like ,
Caseaddr[7:0]
Reg1 : reg <= '1';
Reg2 : reg <= '0';
-
-
Regn : reg <= '1'
I have made a file REG_PKG.v and defined like,
'define 8'b 00000000 Reg1
But still compiler is throwing error saying that, Reg1, Reg2 etc is not declared.
Here, i have compiled the Package file and added line `include in my original code.
Please help me, how to make a constants file in Verilog similar to VHDL.
regards,
freak