Verilog - netlist Error

[ee1]

Hi,
while reading the verilog I am getting this Error:
"Error: Expected '(' but found '['"
for this line:
inv_lib_cell U1[2:0] ( .A(n2[2:0]), .Y(n1[2:0]));

can someone pls tell me whats wrong?..

Thanks!

 

[ljxpjpjljx]

have you checked whether A and Y is 1 bit width or 3 bit width?

 

[ee1]

How can i check this?

 

[jeet_asic]

Post full program . If would be easier to sort out error.

 

[dave_59]

What tool is giving you this error? It possible it doesn't support arrays of instances, something that was added to Verilog in 1995! You can try removing each set of []'s and see if you get a different error