Verilog how to lock value?

[adgjl40112]

Hi, guys. I have a verilog problem.
In verilog, how do we lock the value?
What I mean is that I have a counter, and I want to increase it only one time.
If I put counter in the sequential block . It will increase when every posedge clock arrive. It's not what I desired. I want to increase the counter again until next enable signal arrive.

How can I achieve this?

For example, A is my input

always@(posedge clk)
begin
   if (A)
       counter <= counter + 1;
end

It will increase the counter when every psoedge clk arrive.
But I want the counter only increase once. And it increase again when A signal is change.
Please help

 

[pavan.ps]

Can you tell the clock u use to generate the A signal?
Say, if u generate the A signal with a lesser clock than clk then counter increments many times.

 

[saurabhs]

If i understand correctly ur prob

I think just change the sensitivity list

Always @( signal on which u want to execute always block )

 

[mux_master]

What is the A signal? A 1 bit value? The way your counter is setup now it will increase on the positive edge of the clock whenever A is not equal to 0. You may need to refine your if logic.

For instance, create a register for the previous value of A and register it every clock cycle. Then increment your count when A != A_prev.

 

[FvM]

Sounds like a bad explanation of a simple intention. Do you want to count each edge of signal A? Synchronous edge detection can achieve it easily:

reg as1,as0;
always@(posedge clk) 
begin
   as0 <= A;
   as1 <= as0;  
   if (as0 && !as1) 
       counter <= counter + 1; 
end