verilog code test with Spartan 3 AN

[krivan]

verilog code for spartan 3 kit

Hi,

I want to test my bus protocol written in verilog with my Spartan 3-AN Starter Kit.

I synthesized, mapped, placed and routed it with ISE 9.2 and I downloaded it. I used the boundary scan option.

The question is: how can I send data into this module and check its response with oscilloscope?

 

[j_andr]

verilog code for storing data into memory

/.../how can I send data into this module and check its response/.../

create an extra top level where you connect a test data source
to your design and - eventually - a kind of output checker;
the test data source can be either some logic or a memory
filled with test patterns;
to check the response use ChipScope [xilinx logic analyzer]
rather then a scope;
--

 

[krivan]

verilog i2c slave

I'm trying to test an i2c slave. So should I download the testbench to the fpga, or should I find an i2c master and download it? I have no experience about it. Regarding the ChipScope, thanks for the idea!

 

[pwq1999]

i2c master code verilog

maybe you could use an external device as a I2c master,and communicate with the fpga(your I2c Slave). Chipscope is a good tool when using xilinx fpga.

 

[j_andr]

how to test a memory in verilog

your testbench most probably can not be synthesied so you can not
'load' it into the device;
but you have simulations waveforms, right ?
create with xilinx coregen a memory 2-bit wide and a couple of Kwords deep,
the memory will keep levels of SDA and SDC lines which you will connect
as inputs to your i2c slave;
create a counter which will address your memory;
fill the memory with desired pattern - same as you can see on your simulator
waveforms;
e.g:

SDA[mem bit0]        1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0  .... 0000111
SCL[mem bit1]        1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0  .... 0011111
                         ^            ^ ^ ^                      ^
                     start_bit      data transfer          stop bit

this way you can create 'self-testing' design;
if you find an i2c master and integrate it with your slave you will still need
something that controls the master, something which sends data to the master
to make it 'talk' to the slave ...
--

 

[naz56]

verilog i2c

eeprom will b master and fpga will be slave?

wt is the concept of master and slave?

thanx