[SOLVED] Verilog code for hex to bcd conversion

[dhaval4987]

I have ABSOLUTELY no background in verilog (or digital designs for that matter). Just for ease of simulations of larger analog systems, I thought it would be better to provide hex inputs instead of long chains of binary values. So I decided to write veriloga code that spectre can understand. I know veriloga is superset of verilog and so i wrote the basic code in verilog.

Like I said, I am not a digital designer and from internet tutorials, I picked basic instructions about verilog in an hour and wrote this. Of course this is wrong and gives error.

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Code Verilog - [expand]
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module hex2bcd(bcd);
output [31:0] bcd;
wire [31:0] bcd;
wire [31:0] code;
parameter code 32'hFFFFFFFF;
 
always
bcd[0] = code & 'b01;
code = code>>1;
 
bcd[1] = code & 'b01;
code = code>>1;
 
bcd[2] = code & 'b01;
code = code>>1;
 
bcd[3] = code & 'b01;
code = code>>1;
 
bcd[4] = code & 'b01;
code = code>>1;
 
bcd[5] = code & 'b01;
code = code>>1;
 
bcd[6] = code & 'b01;
code = code>>1;
 
bcd[7] = code & 'b01;
code = code>>1;
 
bcd[8] = code & 'b01;
code = code>>1;
 
bcd[9] = code & 'b01;
code = code>>1;
 
bcd[10] = code & 'b01;
code = code>>1;
 
bcd[11] = code & 'b01;
code = code>>1;
 
bcd[12] = code & 'b01;
code = code>>1;
 
bcd[13] = code & 'b01;
code = code>>1;
 
bcd[14] = code & 'b01;
code = code>>1;
 
bcd[15] = code & 'b01;
code = code>>1;
 
bcd[16] = code & 'b01;
code = code>>1;
 
bcd[17] = code & 'b01;
code = code>>1;
 
bcd[18] = code & 'b01;
code = code>>1;
 
bcd[19] = code & 'b01;
code = code>>1;
 
bcd[20] = code & 'b01;
code = code>>1;
 
bcd[21] = code & 'b01;
code = code>>1;
 
bcd[22] = code & 'b01;
code = code>>1;
 
bcd[23] = code & 'b01;
code = code>>1;
 
bcd[24] = code & 'b01;
code = code>>1;
 
bcd[25] = code & 'b01;
code = code>>1;
 
bcd[26] = code & 'b01;
code = code>>1;
 
bcd[27] = code & 'b01;
code = code>>1;
 
bcd[28] = code & 'b01;
code = code>>1;
 
bcd[29] = code & 'b01;
code = code>>1;
 
bcd[30] = code & 'b01;
code = code>>1;
 
bcd[31] = code & 'b01;
code = code>>1;
endmodule

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What am I doing wrong?

 

[andre_luis]

Of course this is wrong and gives error

In addition to having named the variable bcd either as wire and output with the same name (which I presume is not allowed), what other errors have been identified by compiler?

 

[FvM]

At first sight, the code function can shortened as bcd = code, because it simply performs a bit-by-bit copy. But what did you want to achieve?

 

[ads-ee]

you have a whole bunch of assignments that are all incorrectly done as assignment have to either be done using the assign keyword or done within an always/intial block. If you want to do these assignments as shown, then you have to have to use the always with a begin end block.
e.g.

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Code Verilog - [expand]
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2
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always @* begin // @* makes the block sensitive to any changes on any of the inputs to the block
  //... assignment statements
end

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Just assigning bcd = code won't convert from hex to bcd.
Hex has numbers from 0000-1111 (0x0 to 0xF)
BCD has numbers from 0000-1001 (0x0 to 0x9) there is no 0xA-0xF

You need to perform the shift and add3 algorithm to do the conversion.

- - - Updated - - -

I get the impression you are trying to get a 32-bit number to be readable as a decimal value.

If this is the case you should just make the simulation display the 32-bit number as an unsigned decimal value or force the simulation to display the value as decimal to the transcript/log window using the $display system task.
e.g.

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Code Verilog - [expand]
1
$display ("My hex value: %h,  the equivalent unsigned decimal %d", hex, {1'b0,dec});

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[dhaval4987]

I see some of the mistakes I have made in writing this. Thank you everyone. I will try and fix those!

- - - Updated - - -

Nah,

I am trying to write a hex vector in input for a system which can only take binary bits as inputs. I want to define a box in verilog which will take a hex input from user and will parse it into equivalent binary bits to the system.

 

[FvM]

No recoding needed to display binary numbers in hex format, just map each four-bit nibble to characters 0 - F.

 

[ads-ee]

Nah,

I am trying to write a hex vector in input for a system which can only take binary bits as inputs. I want to define a box in verilog which will take a hex input from user and will parse it into equivalent binary bits to the system.

Hex vector input? Do you mean a hex input file?

I'm not sure exactly how you expect to use this "user interface". Verilog/VerilogA isn't a user interface language it's a modeling language for simulating. I'm not sure how you expect someone to enter hex inputs and parse them, Verilog doesn't have support for taking input from the keyboard (or at least none that I've found in the LRM). Also as FvM pointed out Hex to binary is simply converting 0-F to 0000-1111. Unfortunately your thread title says you're trying to convert from hex to bcd.