Verilog code for 10T SRAM???

[nagavikasch]

Hi everyone,

Can anyone please tell me how to write a verilog/vhdl code for 10T SRAM??
We trying to simulate it through Xilinx..
Please do reply as soon as possible.

Thanks and Regards,
Naga Vikas

 

[ads-ee]

You're asking something that isn't normally used by anyone that I know of. If you want to model a 10T SRAM cell, I recommend you use SPICE or one of it's derivatives not Verilog. But if you can't be swayed then look at this link.
https://www.asic-world.com/verilog/gate1.html

I don't think there is an equivalent in VHDL that doesn't involve some custom designed library or VHDL-AMS.

In either case I'm not sure Xilinx tools even support the nmos, pmos, etc. switch primatives.

Regards