Joel_Damato
Newbie level 3
Hi,
For that source code:
I used Yosys to generate rtl. It gave me this:
I annotated the code so that you can see where my interrogations lie.
Would you consider it is a reasonable rtl code?
Thanks
For that source code:
Code:
module top(input clk, input led, output to_port1,output [24:0] to_port2);
reg ctr = 0;
reg[24:0] counter = 2;
always@(posedge clk) begin
if (ctr == 1) begin
ctr <= 0;
counter <= counter + 1;
end
else
ctr <= 1;
end
assign led = ctr;
assign to_port1 = led;
assign to_port2 = counter;
endmodule
I used Yosys to generate rtl. It gave me this:
Code:
/* Generated by Yosys 0.8 (git sha1 UNKNOWN, clang 7.0.2 -fPIC -Os) */
(* src = "x.v:1" *)
module top(clk, led, to_port1, to_port2);
(* src = "x.v:5" *)
reg [24:0] _0_;
(* src = "x.v:5" *)
reg _1_;
(* src = "x.v:4" *)
reg [24:0] _2_;
(* src = "x.v:3" *)
reg _3_;
(* src = "x.v:8" *)
wire [31:0] _4_;
(* src = "x.v:6" *)
wire _5_;
(* src = "x.v:1" *)
input clk;
(* src = "x.v:4" *)
reg [24:0] counter;
(* src = "x.v:3" *)
reg ctr;
(* src = "x.v:1" *)
input led;
(* src = "x.v:1" *)
output to_port1;
(* src = "x.v:1" *)
output [24:0] to_port2;
assign _4_ = counter + (* src = "x.v:8" *) 32'd1;
assign _5_ = ctr == (* src = "x.v:6" *) 32'd1;
always @* begin
_3_ = 1'h0;
end
always @* begin /*useless?*/
end
always @({ }) begin
ctr <= _3_;
end
always @* begin
_2_ = 25'h0000002; /* proper way to initialize a value?
end
always @* begin /*useless?*/
end
always @({ }) begin
counter <= _2_; /* _2_ is always equal to 2, no?*/
end
always @* begin
_1_ = ctr;
_0_ = counter;
casez (_5_) /* counter overflow management */
1'h1:
begin
_1_ = 1'h0;
_0_ = _4_[24:0];
end
default:
_1_ = 1'h1;
endcase
end
always @(posedge clk) begin
ctr <= _1_;
counter <= _0_;
end
assign led = ctr;
assign to_port1 = led;
assign to_port2 = counter;
endmodule
I annotated the code so that you can see where my interrogations lie.
Would you consider it is a reasonable rtl code?
Thanks