verilog arithmetic

[KingMoshe]

Hi All,
What will happen if I will do the following operation?

reg [15:0] NUM1;
reg [15:0] NUM2;
NUM1 <= NUM2*16'd1064/16'd100;

The result of "NUM2*16'd1064/16'd100" not always integer.
Please see that if NUM1 = 100 , so NUM1 * 1064 = 106400 and 16 bit register is too small, do the actions (*1064/100) occur together or in two stages?

Thanks,
Moshe.

 

[danadakk]

A note on synthesis here -

Division in verilog

I am teaching myself verilog. The book I am following stated in the introduction chapters that to perform division we use the '/' operator or '%' operator. In later chapters it's saying that divisi...

stackoverflow.com

Not an expert here but <= are non blocking statements, evaluated at end of time step.

Verilog Blocking & Non-Blocking

Blocking Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block. module tb; reg [7:0] a, b, c, d, e; initial begin a = 8'hDA; $display ("[%0t] a=0x%0h b

www.chipverify.com

Regards, Dana.

 

[FvM]

Expression are evaluated left to right, bit width is generally determined by the operands (self-determined) and in some cases by the left hand side (context-determined), e.g. if it's assigned to a wider variable. Because right hand side is also 16 bit wide, the multiplication is trunacted to 16 bit.

The original expression is synthesized this way

To avoid truncation of the multiplication, you can extend the width of the first constant

NUM1 <= NUM2*27'd1064/16'd100;

Synthesis result changes respectively

Notice that the division operation is very ineffective in hardware synthesis. You probably want to replace it with fixed point multiplication.

NUM1 <= NUM2*26'd681>>6;

 

[dave_59]

Expression get evaluated by the rules described in section 11 of the IEEE 1800-2017 LRM. (There is no difference between Verilog and SystemVerilog here) Operands get extended to the maximum width of all other operands in the context of the expression before any operations get evaluated. Since all your operands are 16 bits, nothing gets extended.

Multiplication and division have the same precedence and left associativity, That means NUM2*16'd1064 gets evaluated first in a 16-bit context, so the upper 10 bits of that result could get truncated. Then that result gets divided by 16'd100, remainder truncated.

 

[wwfeldman]

the upper 10 bits of that result could get truncated.

do the most significant bits or least significant bit get truncated?

 

[FvM]

Upper = most significant. See also RTL schematic in post #3.

 

[KingMoshe]

NUM1 <= NUM2*26'd681>>6;

Hi,
Can you please explain the code above?

 

[FvM]

I'm substituting NUM2*1064/100 by NUM2*(64*1064/100)/64 to save the divider.