jmarcelold
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Pleas some one can explain me why in the below code, x0_eq is not equal to x1_eq?
`timescale 10ns/1ns
module test;
reg signed [8:0] x0, x1, x0_shifted, x0_eq, x1_eq;
initial begin
x0 = -27;
x0_shifted = x0 >>> 3;
x0_eq = x0_shifted + x0[2];
x1 = -27;
x1_eq = (x1 >>> 3) + x1[2];
#10;
$finish;
end
endmodule
`timescale 10ns/1ns
module test;
reg signed [8:0] x0, x1, x0_shifted, x0_eq, x1_eq;
initial begin
x0 = -27;
x0_shifted = x0 >>> 3;
x0_eq = x0_shifted + x0[2];
x1 = -27;
x1_eq = (x1 >>> 3) + x1[2];
#10;
$finish;
end
endmodule