verilog （ ? : ）expression to VHDL

[lonsta]

Hi, I am considering how to translate a verilog expression to VHDL as :

{carry, phase_acc} <= (carry ? init_phase : 0) + phase_acc + phase_step;

I write some vhdl code like this :

----------
phase_step : in std_logic_vector(11 downto 0);
-------something something-------
signal pha_acc : std_logic_vector(11 downto 0);
signal carry : std_logic;
signal pha_tmp : std_logic_vector(12 downto 0);
---something -------
clock here---
if (carry = '1') then
    pha_tmp <= ('0'&init_phase) + ('0'&phase_acc) + ('0'&phase_step);
    carry <= pha_tmp(12);
    phase_acc <= pha_tmp(11 downto 0);
else
    pha_tmp <=('0'&phase_acc) + ('0'&phase_step);
    carry <= pha_tmp(12);
    phase_acc <= pha_tmp(11 downto 0);
end if;

In verilog, the 'carry' and 'phase_acc' signals refresh the values at every clock, but in VHDL, it seems that carry and phase_acc have to wait for a clock period as there is a pipeline and get the value at the next-next clock edge.
because I don't know how to put two signals together as the signal sinks,e.g. a&b <= c+d is not allowed in VHDL which we can do in verilog using {}.
so, if I want get the carry and phase_acc just next clock, how would I optimise my code, any advice is appreciated...

 

[FvM]

Yes, VHDL doesn't provide a concantenate operation for left-hand-side operators. You can simply write two lines or use an intermediate
variable to hold the full length expression. Sometimes, VHDL is a bit more verbose than Verilog. But the generated code won't be
affected by different assignment styles as long they are functionally equivalent, they can be expected to end up in the same logic
cell mapping.

 

[lonsta]

Yes, VHDL doesn't provide a concantenate operation for left-hand-side operators. You can simply write two lines or use an intermediate
variable to hold the full length expression. Sometimes, VHDL is a bit more verbose than Verilog. But the generated code won't be
affected by different assignment styles as long they are functionally equivalent, they can be expected to end up in the same logic
cell mapping.

Thanks for such a quick reply, I got it I have to write more codes. I just performed a simple simulation and through the simulation it's clear that for verilog code above , carry and phase_acc is refreshed right when the phase_acc changed, but for my VHDL code the data refreshed one clock later just because of one register of pha_tmp.! THen I rewrite my code, substitute the signal pha_tmp with a variable pha_tmp, it's ok, I think it's still the signal/varaiable question.
Thanks for all.[/img]