verifyConnectivity error, Cadence Innovus

[pskol95]

Hello Everyone,
I have IO pads in design, and before streamOut GDS I am getting following error after, verifyConnectivity :

Net VDD, Pin Pin: X/VDD ; Direction: INOUT; Use: POWER;: has an unconnected terminal at (1498.800, 2892.800) (1558.800, 2901.230)
Net VSS, Pin Pin: X/VSS ; Direction: INOUT; Use: GROUND;: has an unconnected terminal at (1498.800, 2903.610) (1558.800, 2914.260)
where X stands for all the IO's in design and 2 corner_cell/VSS.
Net VDD: has special routes with opens at (68.800, 107.800) (2870.300, 2882.580)
Net VDDIO: no routing
Net VSS: has regular routing with opens at (63.340, 2828.800) (73.990, 2889.300)
Net VSSIO: no routing
Net VSS: has special routes with opens at (119.800, 119.800) (2908.800, 2882.580)
Net VSS: has regular routing with opens at (2828.800, 2903.610) (2889.300, 2914.260)
Voilation markers are all around the 4 sides of core boundary ( inside IO pads).

**I have IOFiller's between the pads.
**Pad instantiation in netlist is like: PADCELL INST_NAME ( .PAD( ), .DI( ) ) ; where .PAD is "inout" , DI is "output", without any configuration bits set.

How can I resolve this issue ?

Thanks !

 

[ThisIsNotSam]

verifyConnectivity is not something you should trust. it does a lot of false positives. It is useful to pick up on obvious mistakes, but it gets confused very often. I don't think it understand connections by abutment.

It is better to rely on DRC and LVS