VCDL Verilog-A/AMS Model

[anassar]

veriloga delay

Hi all,


Can anyone kindly provide me with a Verilog-A/AMS model of a voltage-controlled delay line?
I know this is a DISTRIBUTED component, but there might be a good lumped-model approximation for it.

Thanks,
Ahmed

 

[anassar]

delay model veriloga

I found the solution:

One can use the Verilog-A "delay()" function or the Verilog-AMS "absdelay()" function with the maxdelay parameter passed properly and letting the delay value be varying.